dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
The Qualcomm QCS404 platform has several buses that could be controlled and tuned according to the bandwidth demand. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Qualcomm QCS404 Network-On-Chip interconnect driver binding
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-----------------------------------------------------------
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Required properties :
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- compatible : shall contain only one of the following:
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"qcom,qcs404-bimc"
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"qcom,qcs404-pcnoc"
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"qcom,qcs404-snoc"
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- #interconnect-cells : should contain 1
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reg : specifies the physical base address and size of registers
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clocks : list of phandles and specifiers to all interconnect bus clocks
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clock-names : clock names should include both "bus" and "bus_a"
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Example:
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soc {
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...
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bimc: interconnect@400000 {
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reg = <0x00400000 0x80000>;
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compatible = "qcom,qcs404-bimc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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pnoc: interconnect@500000 {
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reg = <0x00500000 0x15080>;
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compatible = "qcom,qcs404-pcnoc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
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<&rpmcc RPM_SMD_PNOC_A_CLK>;
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};
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snoc: interconnect@580000 {
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reg = <0x00580000 0x23080>;
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compatible = "qcom,qcs404-snoc";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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};
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};
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Qualcomm interconnect IDs
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*
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* Copyright (c) 2019, Linaro Ltd.
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* Author: Georgi Djakov <georgi.djakov@linaro.org>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
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#define MASTER_AMPSS_M0 0
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#define MASTER_OXILI 1
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#define MASTER_MDP_PORT0 2
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#define MASTER_SNOC_BIMC_1 3
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#define MASTER_TCU_0 4
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#define SLAVE_EBI_CH0 5
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#define SLAVE_BIMC_SNOC 6
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#define MASTER_SPDM 0
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#define MASTER_BLSP_1 1
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#define MASTER_BLSP_2 2
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#define MASTER_XI_USB_HS1 3
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#define MASTER_CRYPT0 4
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#define MASTER_SDCC_1 5
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#define MASTER_SDCC_2 6
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#define MASTER_SNOC_PCNOC 7
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#define MASTER_QPIC 8
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#define PCNOC_INT_0 9
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#define PCNOC_INT_2 10
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#define PCNOC_INT_3 11
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#define PCNOC_S_0 12
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#define PCNOC_S_1 13
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#define PCNOC_S_2 14
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#define PCNOC_S_3 15
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#define PCNOC_S_4 16
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#define PCNOC_S_6 17
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#define PCNOC_S_7 18
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#define PCNOC_S_8 19
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#define PCNOC_S_9 20
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#define PCNOC_S_10 21
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#define PCNOC_S_11 22
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#define SLAVE_SPDM 23
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#define SLAVE_PDM 24
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#define SLAVE_PRNG 25
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#define SLAVE_TCSR 26
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#define SLAVE_SNOC_CFG 27
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#define SLAVE_MESSAGE_RAM 28
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#define SLAVE_DISP_SS_CFG 29
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#define SLAVE_GPU_CFG 30
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#define SLAVE_BLSP_1 31
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#define SLAVE_BLSP_2 32
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#define SLAVE_TLMM_NORTH 33
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#define SLAVE_PCIE 34
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#define SLAVE_ETHERNET 35
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#define SLAVE_TLMM_EAST 36
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#define SLAVE_TCU 37
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#define SLAVE_PMIC_ARB 38
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#define SLAVE_SDCC_1 39
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#define SLAVE_SDCC_2 40
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#define SLAVE_TLMM_SOUTH 41
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#define SLAVE_USB_HS 42
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#define SLAVE_USB3 43
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#define SLAVE_CRYPTO_0_CFG 44
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#define SLAVE_PCNOC_SNOC 45
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#define MASTER_QDSS_BAM 0
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#define MASTER_BIMC_SNOC 1
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#define MASTER_PCNOC_SNOC 2
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#define MASTER_QDSS_ETR 3
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#define MASTER_EMAC 4
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#define MASTER_PCIE 5
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#define MASTER_USB3 6
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#define QDSS_INT 7
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#define SNOC_INT_0 8
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#define SNOC_INT_1 9
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#define SNOC_INT_2 10
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#define SLAVE_KPSS_AHB 11
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#define SLAVE_WCSS 12
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#define SLAVE_SNOC_BIMC_1 13
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#define SLAVE_IMEM 14
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#define SLAVE_SNOC_PCNOC 15
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#define SLAVE_QDSS_STM 16
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#define SLAVE_CATS_0 17
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#define SLAVE_CATS_1 18
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#define SLAVE_LPASS 19
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#endif
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