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MLK-23600-2 Update ISP and Dewarp clock and power 

update ISP and Dewarp clock and power

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com>
(cherry picked from commit e6031680ba2d67a6961a5da5fc68a913962c66d2)
(cherry picked from commit f5390f2bcbc7cb9fab29605fc2d3cb61373a5800)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
This commit is contained in:
Robby Cai 2020-12-24 20:41:57 +08:00 committed by Andrey Zhizhikin
parent bdb006cad8
commit 1ad71e29f5
1 changed files with 24 additions and 4 deletions
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28
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@ -1810,8 +1810,10 @@
compatible = "fsl,imx8mp-isp";
reg = <0x32e10000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
clock-names = "isp_root";
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "core", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
@ -1824,8 +1826,10 @@
compatible = "fsl,imx8mp-isp";
reg = <0x32e20000 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
clock-names = "isp_root";
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "core", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
@ -1838,6 +1842,14 @@
compatible = "fsl,imx8mp-dwe";
reg = <0x32e30000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "core", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
assigned-clock-rates = <500000000>, <200000000>;
power-domains = <&ispdwp_pd>;
id = <0>;
status = "disabled";
};
@ -1846,6 +1858,14 @@
compatible = "fsl,imx8mp-dwe";
reg = <0x32e30000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "core", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
assigned-clock-rates = <500000000>, <200000000>;
power-domains = <&ispdwp_pd>;
id = <1>;
status = "disabled";
};