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ARM64: dts: imx8qm: enable audio sound card 

enable audio sound card (dsp, amix, asrc, esai, sai, cs42888, wm8960)

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
This commit is contained in:
Shengjiu Wang 2019-08-23 16:34:01 +08:00 committed by Dong Aisheng
parent 3666cde64e
commit 12646937b8
11 changed files with 787 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/freescale/Makefile
View File

@ -32,7 +32,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-max9286.dtb \
imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \
imx8qm-mek-hdmi.dtb
imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-max9286.dtb \
imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \

21
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View File

@ -122,22 +122,6 @@ audio_subsys: bus@59000000 {
<&pd IMX_SC_R_MQS_0>;
};
dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
clocks = <&dsp_lpcg 1>,
<&dsp_ram_lpcg 0>,
<&dsp_lpcg 2>;
clock-names = "ipg", "ocram", "core";
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
reserved-region = <&dsp_reserved>;
status = "disabled";
};
asrc0: asrc@59000000 {
compatible = "fsl,imx8qm-asrc0";
reg = <0x59000000 0x10000>;
@ -421,11 +405,12 @@ audio_subsys: bus@59000000 {
};
amix: amix@59840000 {
compatible = "fsl,imx8qm-amix";
compatible = "fsl,imx8qm-audmix";
reg = <0x59840000 0x10000>;
clocks = <&amix_lpcg 0>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_AMIX>;
dais = <&sai4>, <&sai5>;
status = "disabled";
};
@ -565,7 +550,6 @@ audio_subsys: bus@59000000 {
clock-output-names = "sai4_lpcg_mclk",
"sai4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_4>;
status = "disabled";
};
sai5_lpcg: clock-controller@59c30000 {
@ -578,7 +562,6 @@ audio_subsys: bus@59000000 {
clock-output-names = "sai5_lpcg_mclk",
"sai5_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_5>;
status = "disabled";
};
amix_lpcg: clock-controller@59c40000 {

126
arch/arm64/boot/dts/freescale/imx8qm-mek-dsp.dts Normal file
View File

@ -0,0 +1,126 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2018
#include "imx8qm-mek-rpmsg.dts"
/ {
sound-cs42888 {
status = "disabled";
};
sound-wm8960 {
status = "disabled";
};
dspaudio: dspaudio {
compatible = "fsl,dsp-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
status = "okay";
};
sound-dsp {
compatible = "fsl,imx-dsp-audio";
model = "dsp-audio";
cpu-dai = <&dspaudio>;
audio-codec = <&cs42888>;
audio-platform = <&dsp>;
};
};
&edma0 {
compatible = "fsl,imx8qm-edma";
reg = <0x59280000 0x10000>, /* spdif0 rx */
<0x59290000 0x10000>, /* spdif0 tx */
<0x592c0000 0x10000>, /* sai0 rx */
<0x592d0000 0x10000>, /* sai0 tx */
<0x592e0000 0x10000>, /* sai1 rx */
<0x592f0000 0x10000>, /* sai1 tx */
<0x59350000 0x10000>,
<0x59370000 0x10000>;
#dma-cells = <3>;
shared-interrupt;
dma-channels = <8>;
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
"edma2-chan21-tx", /* gpt5 */
"edma2-chan23-rx"; /* gpt7 */
status = "okay";
};
&dsp {
compatible = "fsl,imx8qm-dsp-v1";
reserved-region = <&dsp_reserved>;
reg = <0x556e8000 0x88000>;
clocks = <&esai0_lpcg 1>,
<&esai0_lpcg 0>,
<&asrc0_lpcg 0>,
<&asrc0_lpcg 1>,
<&aud_pll_div0_lpcg 0>,
<&aud_pll_div1_lpcg 0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>;
clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem",
"asrck_0", "asrck_1", "asrck_2", "asrck_3";
assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>,
<&esai0_lpcg 0>;
assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_IRQSTR_DSP>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>,
<&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_DMA_2_CH6>,
<&pd IMX_SC_R_DMA_2_CH7>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>,
<&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_DMA_2_CH0>,
<&pd IMX_SC_R_DMA_2_CH1>,
<&pd IMX_SC_R_DMA_2_CH2>,
<&pd IMX_SC_R_DMA_2_CH3>,
<&pd IMX_SC_R_DMA_2_CH4>,
<&pd IMX_SC_R_DMA_2_CH5>;
status = "okay";
};
&esai0 {
status = "disabled";
};
&asrc0 {
status = "disabled";
};
&sai1 {
status = "disabled";
};
&wm8960 {
status = "disabled";
};
&cs42888 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};

31
arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts
View File

@ -16,6 +16,35 @@
gpio-controller;
#gpio-cells = <2>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>;
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
power-domain-names = "pd_mclk_out_0",
"pd_audio_clk_0",
"pd_audio_clk_1",
"pd_audio_clk_0",
"pd_audio_clk_1";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
fsl,txs-rxm;
status = "okay";
};
};
&cm41_i2c_lpcg {
@ -76,4 +105,4 @@
&uart2_lpcg {
status = "disabled";
};
};

193
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -176,6 +176,59 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound-cs42888 {
compatible = "fsl,imx8qm-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
esai-controller = <&esai0>;
audio-codec = <&cs42888>;
asrc-controller = <&asrc0>;
status = "okay";
};
sound-wm8960 {
compatible = "fsl,imx7d-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
audio-codec = <&wm8960>;
codec-master;
/*
* hp-det = <hp-det-pin hp-det-polarity>;
* hp-det-pin: JD1 JD2 or JD3
* hp-det-polarity = 0: hp detect high for headphone
* hp-det-polarity = 1: hp detect high for speaker
*/
hp-det = <2 0>;
hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "Main MIC",
"RINPUT2", "Main MIC",
"Mic Jack", "MICB",
"Main MIC", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
};
&adc0 {
@ -199,6 +252,35 @@
gpio-controller;
#gpio-cells = <2>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>;
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
power-domain-names = "pd_mclk_out_0",
"pd_audio_clk_0",
"pd_audio_clk_1",
"pd_audio_clk_0",
"pd_audio_clk_1";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
fsl,txs-rxm;
status = "okay";
};
};
&cm41_intmux {
@ -226,6 +308,67 @@
status = "okay";
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&amix {
status = "okay";
};
&esai0 {
compatible = "fsl,imx8qm-esai";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&esai0_lpcg 0>;
assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
fsl,txm-rxs;
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&sai6 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai6_lpcg 0>;
assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&sai7 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai7_lpcg 0>;
assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&i2c1_lvds0 {
#address-cells = <1>;
#size-cells = <0>;
@ -607,6 +750,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
wlf,shared-lrclk;
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};
};
&isi_0 {
@ -722,6 +879,17 @@
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
>;
};
pinctrl_cm41_i2c: cm41i2cgrp {
fsl,pins = <
IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c
@ -735,6 +903,21 @@
>;
};
pinctrl_esai0: esai0grp {
fsl,pins = <
IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040
IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040
IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040
IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040
IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040
IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040
IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040
IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040
IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040
IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
@ -879,6 +1062,16 @@
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040
IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000040
IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040
IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060
IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021

402
arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
View File

@ -4,18 +4,11 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
/*
* FIXME: doc error? Can't access this LPCG on QM and the
* driver actually is not using it currently
*/
&dsp_lpcg {
status = "disabled";
};
&dsp_ram_lpcg {
status = "disabled";
};
/delete-node/ &acm;
/delete-node/ &sai4;
/delete-node/ &sai5;
/delete-node/ &sai4_lpcg;
/delete-node/ &sai5_lpcg;
/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */
&edma0{
@ -94,3 +87,388 @@
"edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */
"edma3-chan10-tx"; /* sai7 */
};
&asrc0 {
clocks = <&asrc0_lpcg 0>,
<&asrc0_lpcg 1>,
<&aud_pll_div0_lpcg 0>,
<&aud_pll_div1_lpcg 0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>;
power-domains = <&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_DMA_2_CH0>,
<&pd IMX_SC_R_DMA_2_CH1>,
<&pd IMX_SC_R_DMA_2_CH2>,
<&pd IMX_SC_R_DMA_2_CH3>,
<&pd IMX_SC_R_DMA_2_CH4>,
<&pd IMX_SC_R_DMA_2_CH5>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&esai0 {
power-domains = <&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_DMA_2_CH6>,
<&pd IMX_SC_R_DMA_2_CH7>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&spdif0 {
power-domains = <&pd IMX_SC_R_SPDIF_0>,
<&pd IMX_SC_R_DMA_2_CH8>,
<&pd IMX_SC_R_DMA_2_CH9>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&sai0 {
power-domains = <&pd IMX_SC_R_SAI_0>,
<&pd IMX_SC_R_DMA_2_CH12>,
<&pd IMX_SC_R_DMA_2_CH13>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&sai1 {
power-domains = <&pd IMX_SC_R_SAI_1>,
<&pd IMX_SC_R_DMA_2_CH14>,
<&pd IMX_SC_R_DMA_2_CH15>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&sai2 {
power-domains = <&pd IMX_SC_R_SAI_2>,
<&pd IMX_SC_R_DMA_2_CH16>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&sai3 {
power-domains = <&pd IMX_SC_R_SAI_3>,
<&pd IMX_SC_R_DMA_2_CH17>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&asrc1 {
clocks = <&asrc1_lpcg 0>,
<&asrc1_lpcg 1>,
<&aud_pll_div0_lpcg 0>,
<&aud_pll_div1_lpcg 0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>;
power-domains = <&pd IMX_SC_R_ASRC_1>,
<&pd IMX_SC_R_DMA_3_CH0>,
<&pd IMX_SC_R_DMA_3_CH1>,
<&pd IMX_SC_R_DMA_3_CH2>,
<&pd IMX_SC_R_DMA_3_CH3>,
<&pd IMX_SC_R_DMA_3_CH4>,
<&pd IMX_SC_R_DMA_3_CH5>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
};
&amix {
dais = <&sai6>, <&sai7>;
};
&asrc0_lpcg {
clocks = <&audio_ipg_clk>,
<&audio_ipg_clk>;
bit-offset = <0 8>;
clock-output-names = "asrc0_lpcg_ipg_clk",
"asrc0_lpcg_mem_clk";
};
&esai0_lpcg {
bit-offset = <16 0>;
clock-output-names = "esai0_lpcg_extal_clk",
"esai0_lpcg_ipg_clk";
};
&spdif0_lpcg {
bit-offset = <20 16>;
clock-output-names = "spdif0_lpcg_tx_clk",
"spdif0_lpcg_gclkw";
};
&sai0_lpcg {
bit-offset = <16 0>;
clock-output-names = "sai0_lpcg_mclk",
"sai0_lpcg_ipg_clk";
};
&sai1_lpcg {
bit-offset = <16 0>;
clock-output-names = "sai1_lpcg_mclk",
"sai1_lpcg_ipg_clk";
};
&sai2_lpcg {
bit-offset = <16 0>;
clock-output-names = "sai2_lpcg_mclk",
"sai2_lpcg_ipg_clk";
};
&sai3_lpcg {
bit-offset = <16 0>;
clock-output-names = "sai3_lpcg_mclk",
"sai3_lpcg_ipg_clk";
};
&asrc1_lpcg {
clocks = <&audio_ipg_clk>,
<&audio_ipg_clk>;
bit-offset = <0 8>;
clock-output-names = "asrc1_lpcg_ipg_clk",
"asrc1_lpcg_mem_clk";
};
&mqs0_lpcg {
bit-offset = <16 0>;
clock-output-names = "mqs0_lpcg_mclk",
"mqs0_lpcg_ipg_clk";
};
&audio_subsys {
acm: acm@59e00000 {
compatible = "nxp,imx8qm-acm";
reg = <0x59e00000 0x1D0000>;
#clock-cells = <1>;
power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_MCLK_OUT_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>,
<&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_ASRC_1>,
<&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_ESAI_1>,
<&pd IMX_SC_R_SAI_0>,
<&pd IMX_SC_R_SAI_1>,
<&pd IMX_SC_R_SAI_2>,
<&pd IMX_SC_R_SAI_3>,
<&pd IMX_SC_R_SAI_4>,
<&pd IMX_SC_R_SAI_5>,
<&pd IMX_SC_R_SAI_6>,
<&pd IMX_SC_R_SAI_7>,
<&pd IMX_SC_R_SPDIF_0>,
<&pd IMX_SC_R_SPDIF_1>,
<&pd IMX_SC_R_MQS_0>;
};
sai4: sai@59080000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59080000 0x10000>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai4_lpcg 1>,
<&clk_dummy>,
<&sai4_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx";
dmas = <&edma0 18 0 1>;
fsl,dataline = <0 0xf 0x0>;
power-domains = <&pd IMX_SC_R_SAI_4>,
<&pd IMX_SC_R_DMA_2_CH18>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
status = "disabled";
};
sai5: sai@59090000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59090000 0x10000>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai5_lpcg 1>,
<&clk_dummy>,
<&sai5_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "tx";
dmas = <&edma0 19 0 0>;
fsl,dataline = <0 0x0 0xf>;
power-domains = <&pd IMX_SC_R_SAI_5>,
<&pd IMX_SC_R_DMA_2_CH19>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
status = "disabled";
};
esai1: esai@59810000 {
compatible = "fsl,imx8qm-esai";
reg = <0x59810000 0x10000>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&esai1_lpcg 1>,
<&esai1_lpcg 0>,
<&esai1_lpcg 1>,
<&clk_dummy>;
clock-names = "core", "extal", "fsys", "spba";
dmas = <&edma1 6 0 1>, <&edma1 7 0 0>;
dma-names = "rx", "tx";
power-domains = <&pd IMX_SC_R_ESAI_1>,
<&pd IMX_SC_R_DMA_3_CH6>,
<&pd IMX_SC_R_DMA_3_CH7>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
status = "disabled";
};
sai6: sai@59820000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59820000 0x10000>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai6_lpcg 1>,
<&clk_dummy>,
<&sai6_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
power-domains = <&pd IMX_SC_R_SAI_6>,
<&pd IMX_SC_R_DMA_3_CH8>,
<&pd IMX_SC_R_DMA_3_CH9>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
status = "disabled";
};
sai7: sai@59830000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59830000 0x10000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai7_lpcg 1>,
<&clk_dummy>,
<&sai7_lpcg 0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "tx";
dmas = <&edma1 10 0 0>;
power-domains = <&pd IMX_SC_R_SAI_7>,
<&pd IMX_SC_R_DMA_3_CH10>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
status = "disabled";
};
sai4_lpcg: clock-controller@59480000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59480000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
<&audio_ipg_clk>;
bit-offset = <16 0>;
clock-output-names = "sai4_lpcg_mclk",
"sai4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_4>;
status = "disabled";
};
sai5_lpcg: clock-controller@59490000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59490000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
<&audio_ipg_clk>;
bit-offset = <16 0>;
clock-output-names = "sai5_lpcg_mclk",
"sai5_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_5>;
status = "disabled";
};
esai1_lpcg: clock-controller@59c10000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c10000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>,
<&audio_ipg_clk>;
bit-offset = <16 0>;
clock-output-names = "esai1_lpcg_extal_clk",
"esai1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ESAI_1>;
};
sai6_lpcg: clock-controller@59c20000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c20000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
<&audio_ipg_clk>;
bit-offset = <16 0>;
clock-output-names = "sai6_lpcg_mclk",
"sai6_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_6>;
};
sai7_lpcg: clock-controller@59c30000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c30000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
<&audio_ipg_clk>;
bit-offset = <16 0>;
clock-output-names = "sai7_lpcg_mclk",
"sai7_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_7>;
};
};

4
arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
View File

@ -64,7 +64,3 @@
&lsio_mu4 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu13 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

25
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -213,6 +213,7 @@
clk_dummy: clock-dummy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "clk_dummy";
};
@ -412,6 +413,30 @@
wakeup-source;
};
vpu_subsys_dsp: bus@55000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x55000000 0x0 0x55000000 0x1000000>;
dsp: dsp@556e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x556e8000 0x88000>;
clocks = <&dsp_lpcg 1>,
<&dsp_ram_lpcg 0>,
<&dsp_lpcg 2>;
clock-names = "ipg", "ocram", "core";
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
reserved-region = <&dsp_reserved>;
fixup-offset = <0x4000000>;
status = "disabled";
};
};
/* sorted in register address */
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-adma.dtsi"

2
arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2018
#include "imx8qxp-mek.dts"
#include "imx8qxp-mek-rpmsg.dts"
/ {
sound-cs42888 {

7
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -201,13 +201,6 @@
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
sound-amix-sai {
compatible = "fsl,imx-audio-amix";
model = "amix-audio-sai";
dais = <&sai4>, <&sai5>;
amix-controller = <&amix>;
};
};
&cm40_i2c {

19
arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
View File

@ -43,3 +43,22 @@
&i2c3 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
&audio_subsys {
dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
clocks = <&dsp_lpcg 1>,
<&dsp_ram_lpcg 0>,
<&dsp_lpcg 2>;
clock-names = "ipg", "ocram", "core";
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
reserved-region = <&dsp_reserved>;
status = "disabled";
};
};