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dt-bindings: coresight: Change CPU phandle to required property 

Do not assume the affinity to CPU0 if cpu phandle is omitted.
Update the DT binding rules to reflect the same by changing it
to a required property.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/0f7f4105d5ffea6ca4313271f3b3fee69da2106a.1562229018.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sai Prakash Ranjan 2019-07-04 15:23:04 +05:30 committed by Greg Kroah-Hartman
parent a94de2e7a3
commit 1141301c20
2 changed files with 7 additions and 5 deletions
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4
Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
View File

@ -26,8 +26,8 @@ Required properties:
processor core is clocked by the internal CPU clock, so it
is enabled with CPU clock by default.
- cpu : the CPU phandle the debug module is affined to. When omitted
the module is considered to belong to CPU0.
- cpu : the CPU phandle the debug module is affined to. Do not assume it
to default to CPU0 if omitted.
Optional properties:

8
Documentation/devicetree/bindings/arm/coresight.txt
View File

@ -59,6 +59,11 @@ its hardware characteristcs.
* port or ports: see "Graph bindings for Coresight" below.
* Additional required property for Embedded Trace Macrocell (version 3.x and
version 4.x):
* cpu: the cpu phandle this ETM/PTM is affined to. Do not
assume it to default to CPU0 if omitted.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
@ -87,9 +92,6 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
source is considered to belong to CPU0.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR