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ARM: at91/pm_slowclock: rename register to named define
This patch will give a name to ARM registers in the assembly source code. It is done to simplify the code reading and the passing of parameters to functions. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Nicolas Ferre
parent
9e1c0b2ee8
commit
0dcfed1486
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@ -46,17 +46,22 @@
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#define PLLALOCK_TIMEOUT 1000
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#define PLLBLOCK_TIMEOUT 1000
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pmc .req r1
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sdramc .req r2
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tmp1 .req r3
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tmp2 .req r4
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ramc1 .req r5
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/*
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* Wait until master clock is ready (after switching master clock source)
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*/
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.macro wait_mckrdy
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mov r4, #MCKRDY_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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mov tmp2, #MCKRDY_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_MCKRDY
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ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
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tst tmp1, #AT91_PMC_MCKRDY
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beq 1b
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2:
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.endm
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@ -65,12 +70,12 @@
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* Wait until master oscillator has stabilized.
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*/
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.macro wait_moscrdy
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mov r4, #MOSCRDY_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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mov tmp2, #MOSCRDY_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_MOSCS
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ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
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tst tmp1, #AT91_PMC_MOSCS
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beq 1b
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2:
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.endm
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@ -79,12 +84,12 @@
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* Wait until PLLA has locked.
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*/
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.macro wait_pllalock
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mov r4, #PLLALOCK_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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mov tmp2, #PLLALOCK_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_LOCKA
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ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
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tst tmp1, #AT91_PMC_LOCKA
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beq 1b
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2:
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.endm
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@ -93,12 +98,12 @@
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* Wait until PLLB has locked.
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*/
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.macro wait_pllblock
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mov r4, #PLLBLOCK_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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mov tmp2, #PLLBLOCK_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_LOCKB
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ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
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tst tmp1, #AT91_PMC_LOCKB
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beq 1b
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2:
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.endm
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@ -117,55 +122,55 @@ ENTRY(at91_slow_clock)
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* R4 = temporary register
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* R5 = Base address of second RAM Controller or 0 if not present
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*/
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ldr r1, .at91_va_base_pmc
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ldr r2, .at91_va_base_sdramc
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ldr r5, .at91_va_base_ramc1
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ldr pmc, .at91_va_base_pmc
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ldr sdramc, .at91_va_base_sdramc
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ldr ramc1, .at91_va_base_ramc1
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/* Drain write buffer */
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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#ifdef CONFIG_ARCH_AT91RM9200
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/* Put SDRAM in self-refresh mode */
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mov r3, #1
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str r3, [r2, #AT91_SDRAMC_SRR]
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mov tmp1, #1
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str tmp1, [sdramc, #AT91_SDRAMC_SRR]
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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/* prepare for DDRAM self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, #AT91_DDRSDRC_LPCB
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orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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str tmp1, .saved_sam9_lpr
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bic tmp1, #AT91_DDRSDRC_LPCB
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orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* figure out if we use the second ram controller */
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cmp r5, #0
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ldrne r4, [r5, #AT91_DDRSDRC_LPR]
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strne r4, .saved_sam9_lpr1
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bicne r4, #AT91_DDRSDRC_LPCB
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orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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cmp ramc1, #0
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ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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strne tmp2, .saved_sam9_lpr1
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bicne tmp2, #AT91_DDRSDRC_LPCB
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orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* Enable DDRAM self-refresh mode */
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str r3, [r2, #AT91_DDRSDRC_LPR]
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strne r4, [r5, #AT91_DDRSDRC_LPR]
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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#else
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/* Enable SDRAM self-refresh mode */
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ldr r3, [r2, #AT91_SDRAMC_LPR]
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str r3, .saved_sam9_lpr
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ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
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str tmp1, .saved_sam9_lpr
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bic r3, #AT91_SDRAMC_LPCB
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orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_SDRAMC_LPR]
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bic tmp1, #AT91_SDRAMC_LPCB
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orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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#endif
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/* Save Master clock setting */
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ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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str r3, .saved_mckr
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ldr tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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str tmp1, .saved_mckr
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/*
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* Set the Master clock source to slow clock
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*/
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bic r3, r3, #AT91_PMC_CSS
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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@ -175,61 +180,61 @@ ENTRY(at91_slow_clock)
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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mov r3, #0
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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mov tmp1, #0
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str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#endif
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/* Save PLLA setting and disable it */
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ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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str r3, .saved_pllar
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ldr tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
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str tmp1, .saved_pllar
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mov r3, #AT91_PMC_PLLCOUNT
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orr r3, r3, #(1 << 29) /* bit 29 always set */
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str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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mov tmp1, #AT91_PMC_PLLCOUNT
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
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str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
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/* Save PLLB setting and disable it */
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ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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str r3, .saved_pllbr
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ldr tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
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str tmp1, .saved_pllbr
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mov r3, #AT91_PMC_PLLCOUNT
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str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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mov tmp1, #AT91_PMC_PLLCOUNT
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str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
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/* Turn off the main oscillator */
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ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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bic r3, r3, #AT91_PMC_MOSCEN
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str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
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/* Wait for interrupt */
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mcr p15, 0, r0, c7, c0, 4
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mcr p15, 0, tmp1, c7, c0, 4
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/* Turn on the main oscillator */
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ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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orr r3, r3, #AT91_PMC_MOSCEN
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str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
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wait_moscrdy
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/* Restore PLLB setting */
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ldr r3, .saved_pllbr
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str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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ldr tmp1, .saved_pllbr
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str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
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tst r3, #(AT91_PMC_MUL & 0xff0000)
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 1f
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tst r3, #(AT91_PMC_MUL & ~0xff0000)
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 2f
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1:
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wait_pllblock
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2:
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/* Restore PLLA setting */
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ldr r3, .saved_pllar
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str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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ldr tmp1, .saved_pllar
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str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
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tst r3, #(AT91_PMC_MUL & 0xff0000)
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 3f
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tst r3, #(AT91_PMC_MUL & ~0xff0000)
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 4f
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3:
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wait_pllalock
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@ -242,11 +247,11 @@ ENTRY(at91_slow_clock)
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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ldr r3, .saved_mckr
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tst r3, #AT91_PMC_PRES
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ldr tmp1, .saved_mckr
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tst tmp1, #AT91_PMC_PRES
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beq 2f
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and r3, r3, #AT91_PMC_PRES
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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and tmp1, tmp1, #AT91_PMC_PRES
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str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#endif
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@ -254,8 +259,8 @@ ENTRY(at91_slow_clock)
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/*
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* Restore master clock setting
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*/
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2: ldr r3, .saved_mckr
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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2: ldr tmp1, .saved_mckr
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str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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@ -263,18 +268,18 @@ ENTRY(at91_slow_clock)
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/* Do nothing - self-refresh is automatically disabled. */
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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/* Restore LPR on AT91 with DDRAM */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_DDRSDRC_LPR]
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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/* if we use the second ram controller */
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cmp r5, #0
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ldrne r4, .saved_sam9_lpr1
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strne r4, [r5, #AT91_DDRSDRC_LPR]
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cmp ramc1, #0
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ldrne tmp2, .saved_sam9_lpr1
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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#else
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/* Restore LPR on AT91 with SDRAM */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_SDRAMC_LPR]
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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#endif
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/* Restore registers, and return */
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