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ARM64: dts: meson: add MMC resets

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Add reset lines to the mmc controllers of the meson gx and axg SoCs

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Jerome Brunet 2018-04-26 12:41:19 +02:00 committed by Kevin Hilman
parent 5e395e1466
commit 098e530362
3 changed files with 10 additions and 1 deletions
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3
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
/ {
compatible = "amlogic,meson-axg";
@ -137,6 +138,7 @@
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_c: mmc@7000 {
@ -148,6 +150,7 @@
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
};

3
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -715,6 +715,7 @@
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
};
&sd_emmc_b {
@ -722,6 +723,7 @@
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
&sd_emmc_c {
@ -729,6 +731,7 @@
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
&spicc {

5
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -724,13 +724,15 @@
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
&sd_emmc_c {
@ -738,6 +740,7 @@
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
&spicc {