dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs

Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Martin Blumenstingl 2019-07-27 14:04:12 +02:00 committed by Kishon Vijay Abraham I
parent 609488bc97
commit 088e88be5a
2 changed files with 106 additions and 0 deletions

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
"#phy-cells":
const: 1
description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
compatible:
enum:
- lantiq,vrx200-pcie-phy
- lantiq,arx300-pcie-phy
reg:
maxItems: 1
clocks:
items:
- description: PHY module clock
- description: PDI register clock
clock-names:
items:
- const: phy
- const: pdi
resets:
items:
- description: exclusive PHY reset line
- description: shared reset line between the PCIe PHY and PCIe controller
resets-names:
items:
- const: phy
- const: pcie
lantiq,rcu:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the RCU syscon
lantiq,rcu-endian-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: the offset of the endian registers for this PHY instance in the RCU syscon
lantiq,rcu-big-endian-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
big-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
little-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
required:
- "#phy-cells"
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- lantiq,rcu
- lantiq,rcu-endian-offset
- lantiq,rcu-big-endian-mask
additionalProperties: false
examples:
- |
pcie0_phy: phy@106800 {
compatible = "lantiq,vrx200-pcie-phy";
reg = <0x106800 0x100>;
lantiq,rcu = <&rcu0>;
lantiq,rcu-endian-offset = <0x4c>;
lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
big-endian;
clocks = <&pmu 32>, <&pmu 36>;
clock-names = "phy", "pdi";
resets = <&reset0 12 24>, <&reset0 22 22>;
reset-names = "phy", "pcie";
#phy-cells = <1>;
};
...

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5