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ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR

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This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Claudiu Manoil 2015-07-28 17:43:56 +03:00 committed by Shawn Guo
parent d69cb5d7ea
commit 055223d4d2
2 changed files with 40 additions and 0 deletions
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20
arch/arm/boot/dts/ls1021a-qds.dts
View File

@ -124,6 +124,26 @@
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy1c>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet1 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy1d>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet2 {
phy-handle = <&rgmii_phy3>;
phy-connection-type = "rgmii-id";
status = "okay";
};
&i2c0 {
status = "okay";

20
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -122,6 +122,26 @@
};
};
&enet0 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet1 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet2 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
status = "okay";
};
&i2c0 {
status = "okay";
};