ARM: 8757/1: NOMMU: Support PMSAv8 MPU
ARMv8R/M architecture defines new memory protection scheme - PMSAv8 which is not compatible with PMSAv7. Key differences to PMSAv7 are: - Region geometry is defined by base and limit addresses - Addresses need to be either 32 or 64 byte aligned - No region priority due to overlapping regions are not allowed - It is unified, i.e. no distinction between data/instruction regions - Memory attributes are controlled via MAIR This patch implements support for PMSAv8 MPU defined by ARMv8R/M architecture. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin
Russell King
parent
3c24121039
commit
046835b4aa
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@ -12,6 +12,7 @@
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/* ID_MMFR0 data relevant to MPU */
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#define MMFR0_PMSA (0xF << 4)
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#define MMFR0_PMSAv7 (3 << 4)
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#define MMFR0_PMSAv8 (4 << 4)
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/* MPU D/I Size Register fields */
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#define PMSAv7_RSR_SZ 1
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@ -47,12 +48,43 @@
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#define PMSAv7_AP_PL1RW_PL0R0 (0x2 << 8)
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#define PMSAv7_AP_PL1RW_PL0NA (0x1 << 8)
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#define PMSAv8_BAR_XN 1
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#define PMSAv8_LAR_EN 1
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#define PMSAv8_LAR_IDX(n) (((n) & 0x7) << 1)
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#define PMSAv8_AP_PL1RW_PL0NA (0 << 1)
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#define PMSAv8_AP_PL1RW_PL0RW (1 << 1)
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#define PMSAv8_AP_PL1RO_PL0RO (3 << 1)
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#ifdef CONFIG_SMP
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#define PMSAv8_RGN_SHARED (3 << 3) // inner sharable
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#else
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#define PMSAv8_RGN_SHARED (0 << 3)
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#endif
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#define PMSAv8_RGN_DEVICE_nGnRnE 0
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#define PMSAv8_RGN_NORMAL 1
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#define PMSAv8_MAIR(attr, mt) ((attr) << ((mt) * 8))
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#ifdef CONFIG_CPU_V7M
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#define PMSAv8_MINALIGN 32
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#else
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#define PMSAv8_MINALIGN 64
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#endif
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/* For minimal static MPU region configurations */
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#define PMSAv7_PROBE_REGION 0
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#define PMSAv7_BG_REGION 1
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#define PMSAv7_RAM_REGION 2
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#define PMSAv7_ROM_REGION 3
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/* Fixed for PMSAv8 only */
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#define PMSAv8_XIP_REGION 0
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#define PMSAv8_KERNEL_REGION 1
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/* Maximum number of regions Linux is interested in */
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#define MPU_MAX_REGIONS 16
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@ -63,9 +95,18 @@
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struct mpu_rgn {
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/* Assume same attributes for d/i-side */
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u32 drbar;
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u32 drsr;
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u32 dracr;
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union {
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u32 drbar; /* PMSAv7 */
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u32 prbar; /* PMSAv8 */
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};
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union {
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u32 drsr; /* PMSAv7 */
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u32 prlar; /* PMSAv8 */
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};
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union {
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u32 dracr; /* PMSAv7 */
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u32 unused; /* not used in PMSAv8 */
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};
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};
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struct mpu_rgn_info {
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@ -76,10 +117,15 @@ extern struct mpu_rgn_info mpu_rgn_info;
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#ifdef CONFIG_ARM_MPU
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extern void __init pmsav7_adjust_lowmem_bounds(void);
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extern void __init pmsav8_adjust_lowmem_bounds(void);
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extern void __init pmsav7_setup(void);
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extern void __init pmsav8_setup(void);
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#else
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static inline void pmsav7_adjust_lowmem_bounds(void) {};
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static inline void pmsav8_adjust_lowmem_bounds(void) {};
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static inline void pmsav7_setup(void) {};
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static inline void pmsav8_setup(void) {};
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#endif
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#endif /* __ASSEMBLY__ */
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@ -68,6 +68,14 @@
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#define PMSAv7_RBAR 0x9c
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#define PMSAv7_RASR 0xa0
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#define PMSAv8_RNR 0x98
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#define PMSAv8_RBAR 0x9c
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#define PMSAv8_RLAR 0xa0
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#define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
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#define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
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#define PMSAv8_MAIR0 0xc0
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#define PMSAv8_MAIR1 0xc4
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/* Cache opeartions */
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#define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
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#define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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@ -197,6 +197,8 @@ int main(void)
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DEFINE(MPU_RGN_DRBAR, offsetof(struct mpu_rgn, drbar));
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DEFINE(MPU_RGN_DRSR, offsetof(struct mpu_rgn, drsr));
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DEFINE(MPU_RGN_DRACR, offsetof(struct mpu_rgn, dracr));
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DEFINE(MPU_RGN_PRBAR, offsetof(struct mpu_rgn, prbar));
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DEFINE(MPU_RGN_PRLAR, offsetof(struct mpu_rgn, prlar));
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#endif
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return 0;
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}
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@ -132,6 +132,25 @@ M_CLASS(ldr r3, [r12, 0x50])
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AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
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and r3, r3, #(MMFR0_PMSA) @ PMSA field
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teq r3, #(MMFR0_PMSAv7) @ PMSA v7
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beq 1f
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teq r3, #(MMFR0_PMSAv8) @ PMSA v8
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/*
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* Memory region attributes for PMSAv8:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* NORMAL 001 11111111
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*/
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ldreq r3, =PMSAv8_MAIR(0x00, PMSAv8_RGN_DEVICE_nGnRnE) | \
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PMSAv8_MAIR(0xff, PMSAv8_RGN_NORMAL)
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AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0
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M_CLASS(streq r3, [r12, #PMSAv8_MAIR0])
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moveq r3, #0
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AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1
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M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
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1:
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#endif
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#ifdef CONFIG_CPU_CP15
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/*
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@ -235,6 +254,8 @@ M_CLASS(ldr r0, [r12, 0x50])
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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beq __setup_pmsa_v7
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teq r0, #(MMFR0_PMSAv8) @ PMSA v8
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beq __setup_pmsa_v8
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ret lr
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ENDPROC(__setup_mpu)
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@ -304,6 +325,119 @@ M_CLASS(ldr r0, [r12, #MPU_TYPE])
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ret lr
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ENDPROC(__setup_pmsa_v7)
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ENTRY(__setup_pmsa_v8)
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mov r0, #0
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AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
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M_CLASS(str r0, [r12, #PMSAv8_RNR])
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isb
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#ifdef CONFIG_XIP_KERNEL
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ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start
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ldr r6, =(_exiprom) @ ROM end
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
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AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
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#endif
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ldr r5, =KERNEL_START
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ldr r6, =KERNEL_END
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
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AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
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/* Setup Background: 0x0 - min(KERNEL_START, XIP_PHYS_ADDR) */
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#ifdef CONFIG_XIP_KERNEL
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ldr r6, =KERNEL_START
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ldr r5, =CONFIG_XIP_PHYS_ADDR
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cmp r6, r5
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movcs r6, r5
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#else
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ldr r6, =KERNEL_START
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#endif
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cmp r6, #0
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beq 1f
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mov r5, #0
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2
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AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
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1:
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/* Setup Background: max(KERNEL_END, _exiprom) - 0xffffffff */
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#ifdef CONFIG_XIP_KERNEL
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ldr r5, =KERNEL_END
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ldr r6, =(_exiprom)
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cmp r5, r6
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movcc r5, r6
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#else
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ldr r5, =KERNEL_END
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#endif
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mov r6, #0xffffffff
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3
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AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
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M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)])
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M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
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#ifdef CONFIG_XIP_KERNEL
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/* Setup Background: min(_exiprom, KERNEL_END) - max(KERNEL_START, XIP_PHYS_ADDR) */
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ldr r5, =(_exiprom)
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ldr r6, =KERNEL_END
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cmp r5, r6
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movcs r5, r6
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ldr r6, =KERNEL_START
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ldr r0, =CONFIG_XIP_PHYS_ADDR
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cmp r6, r0
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movcc r6, r0
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sub r6, r6, #1
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bic r6, r6, #(PMSAv8_MINALIGN - 1)
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orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
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orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
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#ifdef CONFIG_CPU_V7M
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/* There is no alias for n == 4 */
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mov r0, #4
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str r0, [r12, #PMSAv8_RNR] @ PRSEL
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isb
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str r5, [r12, #PMSAv8_RBAR_A(0)]
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str r6, [r12, #PMSAv8_RLAR_A(0)]
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#else
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mcr p15, 0, r5, c6, c10, 1 @ PRBAR4
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mcr p15, 0, r6, c6, c10, 2 @ PRLAR4
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#endif
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#endif
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ret lr
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ENDPROC(__setup_pmsa_v8)
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#ifdef CONFIG_SMP
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/*
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* r6: pointer at mpu_rgn_info
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@ -319,6 +453,8 @@ ENTRY(__secondary_setup_mpu)
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and r0, r0, #(MMFR0_PMSA) @ PMSA field
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teq r0, #(MMFR0_PMSAv7) @ PMSA v7
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beq __secondary_setup_pmsa_v7
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teq r0, #(MMFR0_PMSAv8) @ PMSA v8
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beq __secondary_setup_pmsa_v8
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b __error_p
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ENDPROC(__secondary_setup_mpu)
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@ -361,6 +497,33 @@ ENTRY(__secondary_setup_pmsa_v7)
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ret lr
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ENDPROC(__secondary_setup_pmsa_v7)
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ENTRY(__secondary_setup_pmsa_v8)
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ldr r4, [r6, #MPU_RNG_INFO_USED]
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#ifndef CONFIG_XIP_KERNEL
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add r4, r4, #1
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#endif
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mov r5, #MPU_RNG_SIZE
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add r3, r6, #MPU_RNG_INFO_RNGS
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mla r3, r4, r5, r3
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1:
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sub r3, r3, #MPU_RNG_SIZE
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sub r4, r4, #1
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mcr p15, 0, r4, c6, c2, 1 @ PRSEL
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isb
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ldr r5, [r3, #MPU_RGN_PRBAR]
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ldr r6, [r3, #MPU_RGN_PRLAR]
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mcr p15, 0, r5, c6, c3, 0 @ PRBAR
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mcr p15, 0, r6, c6, c3, 1 @ PRLAR
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cmp r4, #0
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bgt 1b
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ret lr
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ENDPROC(__secondary_setup_pmsa_v8)
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_ARM_MPU */
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#include "head-common.S"
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@ -13,6 +13,7 @@
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/mpu.h>
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#include <asm/page.h>
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#include "vmlinux.lds.h"
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@ -148,6 +149,9 @@ SECTIONS
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__init_end = .;
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BSS_SECTION(0, 0, 8)
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#ifdef CONFIG_ARM_MPU
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. = ALIGN(PMSAv8_MINALIGN);
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#endif
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_end = .;
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STABS_DEBUG
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@ -12,6 +12,7 @@
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/mpu.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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@ -54,6 +55,9 @@ SECTIONS
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. = ALIGN(1<<SECTION_SHIFT);
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#endif
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#ifdef CONFIG_ARM_MPU
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. = ALIGN(PMSAv8_MINALIGN);
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#endif
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.text : { /* Real text segment */
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_stext = .; /* Text and read-only data */
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ARM_TEXT
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@ -143,6 +147,9 @@ SECTIONS
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_edata = .;
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BSS_SECTION(0, 0, 0)
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#ifdef CONFIG_ARM_MPU
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. = ALIGN(PMSAv8_MINALIGN);
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#endif
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_end = .;
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STABS_DEBUG
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@ -10,7 +10,7 @@ obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
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ifneq ($(CONFIG_MMU),y)
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obj-y += nommu.o
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obj-$(CONFIG_ARM_MPU) += pmsa-v7.o
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obj-$(CONFIG_ARM_MPU) += pmsa-v7.o pmsa-v8.o
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endif
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obj-$(CONFIG_ARM_PTDUMP_CORE) += dump.o
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@ -107,6 +107,9 @@ static void __init adjust_lowmem_bounds_mpu(void)
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case MMFR0_PMSAv7:
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pmsav7_adjust_lowmem_bounds();
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break;
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case MMFR0_PMSAv8:
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pmsav8_adjust_lowmem_bounds();
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break;
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default:
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break;
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}
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@ -120,6 +123,9 @@ static void __init mpu_setup(void)
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case MMFR0_PMSAv7:
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pmsav7_setup();
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break;
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case MMFR0_PMSAv8:
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pmsav8_setup();
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break;
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default:
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break;
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}
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@ -0,0 +1,307 @@
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/*
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||||
* Based on linux/arch/arm/pmsa-v7.c
|
||||
*
|
||||
* ARM PMSAv8 supporting functions.
|
||||
*/
|
||||
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/range.h>
|
||||
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/mpu.h>
|
||||
|
||||
#include <asm/memory.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
#include "mm.h"
|
||||
|
||||
#ifndef CONFIG_CPU_V7M
|
||||
|
||||
#define PRSEL __ACCESS_CP15(c6, 0, c2, 1)
|
||||
#define PRBAR __ACCESS_CP15(c6, 0, c3, 0)
|
||||
#define PRLAR __ACCESS_CP15(c6, 0, c3, 1)
|
||||
|
||||
static inline u32 prlar_read(void)
|
||||
{
|
||||
return read_sysreg(PRLAR);
|
||||
}
|
||||
|
||||
static inline u32 prbar_read(void)
|
||||
{
|
||||
return read_sysreg(PRBAR);
|
||||
}
|
||||
|
||||
static inline void prsel_write(u32 v)
|
||||
{
|
||||
write_sysreg(v, PRSEL);
|
||||
}
|
||||
|
||||
static inline void prbar_write(u32 v)
|
||||
{
|
||||
write_sysreg(v, PRBAR);
|
||||
}
|
||||
|
||||
static inline void prlar_write(u32 v)
|
||||
{
|
||||
write_sysreg(v, PRLAR);
|
||||
}
|
||||
#else
|
||||
|
||||
static inline u32 prlar_read(void)
|
||||
{
|
||||
return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
|
||||
}
|
||||
|
||||
static inline u32 prbar_read(void)
|
||||
{
|
||||
return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);
|
||||
}
|
||||
|
||||
static inline void prsel_write(u32 v)
|
||||
{
|
||||
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
|
||||
}
|
||||
|
||||
static inline void prbar_write(u32 v)
|
||||
{
|
||||
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
|
||||
}
|
||||
|
||||
static inline void prlar_write(u32 v)
|
||||
{
|
||||
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static struct range __initdata io[MPU_MAX_REGIONS];
|
||||
static struct range __initdata mem[MPU_MAX_REGIONS];
|
||||
|
||||
static unsigned int __initdata mpu_max_regions;
|
||||
|
||||
static __init bool is_region_fixed(int number)
|
||||
{
|
||||
switch (number) {
|
||||
case PMSAv8_XIP_REGION:
|
||||
case PMSAv8_KERNEL_REGION:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
void __init pmsav8_adjust_lowmem_bounds(void)
|
||||
{
|
||||
phys_addr_t mem_end;
|
||||
struct memblock_region *reg;
|
||||
bool first = true;
|
||||
|
||||
for_each_memblock(memory, reg) {
|
||||
if (first) {
|
||||
phys_addr_t phys_offset = PHYS_OFFSET;
|
||||
|
||||
/*
|
||||
* Initially only use memory continuous from
|
||||
* PHYS_OFFSET */
|
||||
if (reg->base != phys_offset)
|
||||
panic("First memory bank must be contiguous from PHYS_OFFSET");
|
||||
mem_end = reg->base + reg->size;
|
||||
first = false;
|
||||
} else {
|
||||
/*
|
||||
* memblock auto merges contiguous blocks, remove
|
||||
* all blocks afterwards in one go (we can't remove
|
||||
* blocks separately while iterating)
|
||||
*/
|
||||
pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
|
||||
&mem_end, ®->base);
|
||||
memblock_remove(reg->base, 0 - reg->base);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int __init __mpu_max_regions(void)
|
||||
{
|
||||
static int max_regions;
|
||||
u32 mpuir;
|
||||
|
||||
if (max_regions)
|
||||
return max_regions;
|
||||
|
||||
mpuir = read_cpuid_mputype();
|
||||
|
||||
max_regions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
|
||||
|
||||
return max_regions;
|
||||
}
|
||||
|
||||
static int __init __pmsav8_setup_region(unsigned int number, u32 bar, u32 lar)
|
||||
{
|
||||
if (number > mpu_max_regions
|
||||
|| number >= MPU_MAX_REGIONS)
|
||||
return -ENOENT;
|
||||
|
||||
dsb();
|
||||
prsel_write(number);
|
||||
isb();
|
||||
prbar_write(bar);
|
||||
prlar_write(lar);
|
||||
|
||||
mpu_rgn_info.rgns[number].prbar = bar;
|
||||
mpu_rgn_info.rgns[number].prlar = lar;
|
||||
|
||||
mpu_rgn_info.used++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init pmsav8_setup_ram(unsigned int number, phys_addr_t start,phys_addr_t end)
|
||||
{
|
||||
u32 bar, lar;
|
||||
|
||||
if (is_region_fixed(number))
|
||||
return -EINVAL;
|
||||
|
||||
bar = start;
|
||||
lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
|
||||
|
||||
bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED;
|
||||
lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
|
||||
|
||||
return __pmsav8_setup_region(number, bar, lar);
|
||||
}
|
||||
|
||||
static int __init pmsav8_setup_io(unsigned int number, phys_addr_t start,phys_addr_t end)
|
||||
{
|
||||
u32 bar, lar;
|
||||
|
||||
if (is_region_fixed(number))
|
||||
return -EINVAL;
|
||||
|
||||
bar = start;
|
||||
lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
|
||||
|
||||
bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN;
|
||||
lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN;
|
||||
|
||||
return __pmsav8_setup_region(number, bar, lar);
|
||||
}
|
||||
|
||||
static int __init pmsav8_setup_fixed(unsigned int number, phys_addr_t start,phys_addr_t end)
|
||||
{
|
||||
u32 bar, lar;
|
||||
|
||||
if (!is_region_fixed(number))
|
||||
return -EINVAL;
|
||||
|
||||
bar = start;
|
||||
lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
|
||||
|
||||
bar |= PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED;
|
||||
lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
|
||||
|
||||
prsel_write(number);
|
||||
isb();
|
||||
|
||||
if (prbar_read() != bar || prlar_read() != lar)
|
||||
return -EINVAL;
|
||||
|
||||
/* Reserved region was set up early, we just need a record for secondaries */
|
||||
mpu_rgn_info.rgns[number].prbar = bar;
|
||||
mpu_rgn_info.rgns[number].prlar = lar;
|
||||
|
||||
mpu_rgn_info.used++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_CPU_V7M
|
||||
static int __init pmsav8_setup_vector(unsigned int number, phys_addr_t start,phys_addr_t end)
|
||||
{
|
||||
u32 bar, lar;
|
||||
|
||||
if (number == PMSAv8_KERNEL_REGION)
|
||||
return -EINVAL;
|
||||
|
||||
bar = start;
|
||||
lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
|
||||
|
||||
bar |= PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED;
|
||||
lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
|
||||
|
||||
return __pmsav8_setup_region(number, bar, lar);
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init pmsav8_setup(void)
|
||||
{
|
||||
int i, err = 0;
|
||||
int region = PMSAv8_KERNEL_REGION;
|
||||
|
||||
/* How many regions are supported ? */
|
||||
mpu_max_regions = __mpu_max_regions();
|
||||
|
||||
/* RAM: single chunk of memory */
|
||||
add_range(mem, ARRAY_SIZE(mem), 0, memblock.memory.regions[0].base,
|
||||
memblock.memory.regions[0].base + memblock.memory.regions[0].size);
|
||||
|
||||
/* IO: cover full 4G range */
|
||||
add_range(io, ARRAY_SIZE(io), 0, 0, 0xffffffff);
|
||||
|
||||
/* RAM and IO: exclude kernel */
|
||||
subtract_range(mem, ARRAY_SIZE(mem), __pa(KERNEL_START), __pa(KERNEL_END));
|
||||
subtract_range(io, ARRAY_SIZE(io), __pa(KERNEL_START), __pa(KERNEL_END));
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
/* RAM and IO: exclude xip */
|
||||
subtract_range(mem, ARRAY_SIZE(mem), CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
|
||||
subtract_range(io, ARRAY_SIZE(io), CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_V7M
|
||||
/* RAM and IO: exclude vectors */
|
||||
subtract_range(mem, ARRAY_SIZE(mem), vectors_base, vectors_base + 2 * PAGE_SIZE);
|
||||
subtract_range(io, ARRAY_SIZE(io), vectors_base, vectors_base + 2 * PAGE_SIZE);
|
||||
#endif
|
||||
/* IO: exclude RAM */
|
||||
for (i = 0; i < ARRAY_SIZE(mem); i++)
|
||||
subtract_range(io, ARRAY_SIZE(io), mem[i].start, mem[i].end);
|
||||
|
||||
/* Now program MPU */
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
/* ROM */
|
||||
err |= pmsav8_setup_fixed(PMSAv8_XIP_REGION, CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
|
||||
#endif
|
||||
/* Kernel */
|
||||
err |= pmsav8_setup_fixed(region++, __pa(KERNEL_START), __pa(KERNEL_END));
|
||||
|
||||
|
||||
/* IO */
|
||||
for (i = 0; i < ARRAY_SIZE(io); i++) {
|
||||
if (!io[i].end)
|
||||
continue;
|
||||
|
||||
err |= pmsav8_setup_io(region++, io[i].start, io[i].end);
|
||||
}
|
||||
|
||||
/* RAM */
|
||||
for (i = 0; i < ARRAY_SIZE(mem); i++) {
|
||||
if (!mem[i].end)
|
||||
continue;
|
||||
|
||||
err |= pmsav8_setup_ram(region++, mem[i].start, mem[i].end);
|
||||
}
|
||||
|
||||
/* Vectors */
|
||||
#ifndef CONFIG_CPU_V7M
|
||||
err |= pmsav8_setup_vector(region++, vectors_base, vectors_base + 2 * PAGE_SIZE);
|
||||
#endif
|
||||
if (err)
|
||||
pr_warn("MPU region initialization failure! %d", err);
|
||||
else
|
||||
pr_info("Using ARM PMSAv8 Compliant MPU. Used %d of %d regions\n",
|
||||
mpu_rgn_info.used, mpu_max_regions);
|
||||
}
|
||||
Loading…
Reference in New Issue