clk: qcom: clk-rpmh: Add IPA clock support
The clk-rpmh driver only supports on and off RPMh clock resources. Let's extend the driver by adding support for clocks that are managed by a different type of RPMh resource known as Bus Clock Manager(BCM). The BCM is a configurable shared resource aggregator that scales performance based on a set of frequency points. The Qualcomm IP Accelerator (IPA) clock is an example of a resource that is managed by the BCM and this a requirement from the IPA driver in order to scale its core clock. Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
David Dai
Stephen Boyd
parent
bfeffd1552
commit
04053f4d23
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@ -18,6 +18,31 @@
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#define CLK_RPMH_ARC_EN_OFFSET 0
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#define CLK_RPMH_VRM_EN_OFFSET 4
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#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
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#define BCM_TCS_CMD_VALID_SHIFT 29
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#define BCM_TCS_CMD_VOTE_MASK 0x3fff
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#define BCM_TCS_CMD_VOTE_SHIFT 0
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#define BCM_TCS_CMD(valid, vote) \
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(BCM_TCS_CMD_COMMIT_MASK | \
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((valid) << BCM_TCS_CMD_VALID_SHIFT) | \
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((vote & BCM_TCS_CMD_VOTE_MASK) \
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<< BCM_TCS_CMD_VOTE_SHIFT))
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/**
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* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
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* @unit: divisor used to convert Hz value to an RPMh msg
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* @width: multiplier used to convert Hz value to an RPMh msg
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* @vcd: virtual clock domain that this bcm belongs to
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* @reserved: reserved to pad the struct
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*/
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struct bcm_db {
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__le32 unit;
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__le16 width;
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u8 vcd;
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u8 reserved;
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};
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/**
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* struct clk_rpmh - individual rpmh clock data structure
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* @hw: handle between common and hardware-specific interfaces
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@ -29,6 +54,7 @@
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* @aggr_state: rpmh clock aggregated state
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* @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
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* @valid_state_mask: mask to determine the state of the rpmh clock
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* @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
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* @dev: device to which it is attached
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* @peer: pointer to the clock rpmh sibling
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*/
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@ -42,6 +68,7 @@ struct clk_rpmh {
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u32 aggr_state;
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u32 last_sent_aggr_state;
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u32 valid_state_mask;
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u32 unit;
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struct device *dev;
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struct clk_rpmh *peer;
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};
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@ -98,6 +125,17 @@ static DEFINE_MUTEX(rpmh_clk_lock);
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__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
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CLK_RPMH_VRM_EN_OFFSET, 1, _div)
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#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
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static struct clk_rpmh _platform##_##_name = { \
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.res_name = _res_name, \
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.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
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.div = 1, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpmh_bcm_ops, \
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.name = #_name, \
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}, \
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}
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static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
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{
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return container_of(_hw, struct clk_rpmh, hw);
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@ -210,6 +248,96 @@ static const struct clk_ops clk_rpmh_ops = {
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.recalc_rate = clk_rpmh_recalc_rate,
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};
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static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
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{
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struct tcs_cmd cmd = { 0 };
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u32 cmd_state;
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int ret;
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mutex_lock(&rpmh_clk_lock);
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cmd_state = 0;
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if (enable) {
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cmd_state = 1;
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if (c->aggr_state)
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cmd_state = c->aggr_state;
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}
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if (c->last_sent_aggr_state == cmd_state) {
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mutex_unlock(&rpmh_clk_lock);
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return 0;
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}
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cmd.addr = c->res_addr;
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cmd.data = BCM_TCS_CMD(enable, cmd_state);
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ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
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if (ret) {
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dev_err(c->dev, "set active state of %s failed: (%d)\n",
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c->res_name, ret);
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mutex_unlock(&rpmh_clk_lock);
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return ret;
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}
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c->last_sent_aggr_state = cmd_state;
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mutex_unlock(&rpmh_clk_lock);
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return 0;
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}
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static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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return clk_rpmh_bcm_send_cmd(c, true);
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};
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static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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clk_rpmh_bcm_send_cmd(c, false);
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};
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static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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c->aggr_state = rate / c->unit;
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/*
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* Since any non-zero value sent to hw would result in enabling the
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* clock, only send the value if the clock has already been prepared.
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*/
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if (clk_hw_is_prepared(hw))
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clk_rpmh_bcm_send_cmd(c, true);
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return 0;
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};
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static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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return c->aggr_state * c->unit;
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}
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static const struct clk_ops clk_rpmh_bcm_ops = {
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.prepare = clk_rpmh_bcm_prepare,
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.unprepare = clk_rpmh_bcm_unprepare,
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.set_rate = clk_rpmh_bcm_set_rate,
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.round_rate = clk_rpmh_round_rate,
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.recalc_rate = clk_rpmh_bcm_recalc_rate,
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};
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/* Resource name must match resource id present in cmd-db. */
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DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
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DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
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@ -217,6 +345,7 @@ DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
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DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
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static struct clk_hw *sdm845_rpmh_clocks[] = {
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[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
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@ -231,6 +360,7 @@ static struct clk_hw *sdm845_rpmh_clocks[] = {
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[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
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[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
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[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
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[RPMH_IPA_CLK] = &sdm845_ipa.hw,
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};
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static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
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@ -267,6 +397,8 @@ static int clk_rpmh_probe(struct platform_device *pdev)
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for (i = 0; i < desc->num_clks; i++) {
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u32 res_addr;
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size_t aux_data_len;
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const struct bcm_db *data;
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rpmh_clk = to_clk_rpmh(hw_clks[i]);
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res_addr = cmd_db_read_addr(rpmh_clk->res_name);
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@ -275,6 +407,20 @@ static int clk_rpmh_probe(struct platform_device *pdev)
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rpmh_clk->res_name);
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return -ENODEV;
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}
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data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
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if (IS_ERR(data)) {
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ret = PTR_ERR(data);
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dev_err(&pdev->dev,
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"error reading RPMh aux data for %s (%d)\n",
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rpmh_clk->res_name, ret);
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return ret;
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}
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/* Convert unit from Khz to Hz */
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if (aux_data_len == sizeof(*data))
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rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
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rpmh_clk->res_addr += res_addr;
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rpmh_clk->dev = &pdev->dev;
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@ -18,5 +18,6 @@
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#define RPMH_RF_CLK2_A 9
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#define RPMH_RF_CLK3 10
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#define RPMH_RF_CLK3_A 11
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#define RPMH_IPA_CLK 12
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#endif
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