2018-09-11 04:27:58 +09:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
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/*
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* Register definitions based on mali_midg_regmap.h
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* (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
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*/
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#ifndef __PANFROST_REGS_H__
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#define __PANFROST_REGS_H__
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#define GPU_ID 0x00
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#define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */
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#define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */
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#define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */
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#define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */
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#define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */
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#define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */
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#define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */
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#define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */
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#define GPU_INT_RAWSTAT 0x20
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#define GPU_INT_CLEAR 0x24
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#define GPU_INT_MASK 0x28
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#define GPU_INT_STAT 0x2c
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#define GPU_IRQ_FAULT BIT(0)
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#define GPU_IRQ_MULTIPLE_FAULT BIT(7)
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#define GPU_IRQ_RESET_COMPLETED BIT(8)
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#define GPU_IRQ_POWER_CHANGED BIT(9)
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#define GPU_IRQ_POWER_CHANGED_ALL BIT(10)
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#define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16)
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#define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
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#define GPU_IRQ_MASK_ALL \
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(GPU_IRQ_FAULT |\
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GPU_IRQ_MULTIPLE_FAULT |\
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GPU_IRQ_RESET_COMPLETED |\
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GPU_IRQ_POWER_CHANGED |\
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GPU_IRQ_POWER_CHANGED_ALL |\
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GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\
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GPU_IRQ_CLEAN_CACHES_COMPLETED)
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#define GPU_IRQ_MASK_ERROR \
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( \
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GPU_IRQ_FAULT |\
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GPU_IRQ_MULTIPLE_FAULT)
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#define GPU_CMD 0x30
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#define GPU_CMD_SOFT_RESET 0x01
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2019-06-18 17:16:48 +09:00
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#define GPU_CMD_PERFCNT_CLEAR 0x03
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#define GPU_CMD_PERFCNT_SAMPLE 0x04
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#define GPU_CMD_CLEAN_CACHES 0x07
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#define GPU_CMD_CLEAN_INV_CACHES 0x08
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2018-09-11 04:27:58 +09:00
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#define GPU_STATUS 0x34
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2019-06-18 17:16:48 +09:00
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#define GPU_STATUS_PRFCNT_ACTIVE BIT(2)
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2018-09-11 04:27:58 +09:00
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#define GPU_LATEST_FLUSH_ID 0x38
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2020-09-17 00:01:46 +09:00
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#define GPU_PWR_KEY 0x50 /* (WO) Power manager key register */
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#define GPU_PWR_KEY_UNLOCK 0x2968A819
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#define GPU_PWR_OVERRIDE0 0x54 /* (RW) Power manager override settings */
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#define GPU_PWR_OVERRIDE1 0x58 /* (RW) Power manager override settings */
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2018-09-11 04:27:58 +09:00
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#define GPU_FAULT_STATUS 0x3C
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#define GPU_FAULT_ADDRESS_LO 0x40
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#define GPU_FAULT_ADDRESS_HI 0x44
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2019-06-18 17:16:48 +09:00
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#define GPU_PERFCNT_BASE_LO 0x60
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#define GPU_PERFCNT_BASE_HI 0x64
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#define GPU_PERFCNT_CFG 0x68
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#define GPU_PERFCNT_CFG_MODE(x) (x)
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#define GPU_PERFCNT_CFG_MODE_OFF 0
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#define GPU_PERFCNT_CFG_MODE_MANUAL 1
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#define GPU_PERFCNT_CFG_MODE_TILE 2
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#define GPU_PERFCNT_CFG_AS(x) ((x) << 4)
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#define GPU_PERFCNT_CFG_SETSEL(x) ((x) << 8)
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#define GPU_PRFCNT_JM_EN 0x6c
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#define GPU_PRFCNT_SHADER_EN 0x70
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#define GPU_PRFCNT_TILER_EN 0x74
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#define GPU_PRFCNT_MMU_L2_EN 0x7c
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2018-09-11 04:27:58 +09:00
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#define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */
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#define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
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#define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */
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#define GPU_THREAD_FEATURES 0x0AC /* (RO) Thread features */
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#define GPU_THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that
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* TLS must be allocated for */
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#define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4))
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#define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4))
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#define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
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#define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
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#define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
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#define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
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#define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
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#define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
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#define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
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#define COHERENCY_ACE_LITE BIT(0)
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#define COHERENCY_ACE BIT(1)
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#define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
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#define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
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#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
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#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
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#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
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#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
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#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
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#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
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#define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */
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#define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
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#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
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#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
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#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
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#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
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#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
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#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
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#define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */
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#define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
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#define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
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#define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
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#define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
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#define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
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#define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
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#define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
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#define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */
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#define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
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#define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
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#define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
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#define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
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#define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
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#define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
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#define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
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#define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */
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#define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
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#define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
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#define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
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#define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
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#define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
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#define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
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#define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
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#define GPU_JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific register) */
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#define GPU_SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */
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#define GPU_TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */
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#define GPU_L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */
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/* L2_MMU_CONFIG register */
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#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT 23
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#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT 24
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT 26
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
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#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
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#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT 12
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#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
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#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT 15
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#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
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/* SHADER_CONFIG register */
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#define SC_ALT_COUNTERS BIT(3)
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#define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4)
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#define SC_SDC_DISABLE_OQ_DISCARD BIT(6)
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#define SC_LS_ALLOW_ATTR_TYPES BIT(16)
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#define SC_LS_PAUSEBUFFER_DISABLE BIT(16)
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#define SC_TLS_HASH_ENABLE BIT(17)
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#define SC_LS_ATTR_CHECK_DISABLE BIT(18)
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#define SC_ENABLE_TEXGRD_FLAGS BIT(25)
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/* End SHADER_CONFIG register */
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/* TILER_CONFIG register */
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#define TC_CLOCK_GATE_OVERRIDE BIT(0)
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/* JM_CONFIG register */
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#define JM_TIMESTAMP_OVERRIDE BIT(0)
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#define JM_CLOCK_GATE_OVERRIDE BIT(1)
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#define JM_JOB_THROTTLE_ENABLE BIT(2)
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#define JM_JOB_THROTTLE_LIMIT_SHIFT 3
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#define JM_MAX_JOB_THROTTLE_LIMIT 0x3F
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#define JM_FORCE_COHERENCY_FEATURES_SHIFT 2
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#define JM_IDVS_GROUP_SIZE_SHIFT 16
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#define JM_MAX_IDVS_GROUP_SIZE 0x3F
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/* Job Control regs */
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#define JOB_INT_RAWSTAT 0x1000
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#define JOB_INT_CLEAR 0x1004
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#define JOB_INT_MASK 0x1008
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#define JOB_INT_STAT 0x100c
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#define JOB_INT_JS_STATE 0x1010
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#define JOB_INT_THROTTLE 0x1014
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#define MK_JS_MASK(j) (0x10001 << (j))
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#define JOB_INT_MASK_ERR(j) BIT((j) + 16)
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#define JOB_INT_MASK_DONE(j) BIT(j)
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#define JS_BASE 0x1800
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#define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00)
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#define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04)
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#define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08)
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#define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c)
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#define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10)
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#define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14)
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#define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18)
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#define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c)
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#define JS_COMMAND(n) (JS_BASE + ((n) * 0x80) + 0x20)
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#define JS_STATUS(n) (JS_BASE + ((n) * 0x80) + 0x24)
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#define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x40)
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#define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x44)
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#define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x50)
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#define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x54)
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#define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x58)
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#define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x60)
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#define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x70)
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/* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
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#define JS_CONFIG_START_FLUSH_CLEAN BIT(8)
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#define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8)
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#define JS_CONFIG_START_MMU BIT(10)
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#define JS_CONFIG_JOB_CHAIN_FLAG BIT(11)
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#define JS_CONFIG_END_FLUSH_CLEAN BIT(12)
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#define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12)
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#define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14)
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#define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15)
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#define JS_CONFIG_THREAD_PRI(n) ((n) << 16)
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#define JS_COMMAND_NOP 0x00
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#define JS_COMMAND_START 0x01
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#define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */
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#define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */
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#define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
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#define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
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#define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
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#define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
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#define JS_STATUS_EVENT_ACTIVE 0x08
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/* MMU regs */
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#define MMU_INT_RAWSTAT 0x2000
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#define MMU_INT_CLEAR 0x2004
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#define MMU_INT_MASK 0x2008
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#define MMU_INT_STAT 0x200c
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/* AS_COMMAND register commands */
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#define AS_COMMAND_NOP 0x00 /* NOP Operation */
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#define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
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#define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
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#define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
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#define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs
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(deprecated - only for use with T60x) */
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#define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */
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#define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then
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flush all L2 caches then issue a flush region command to all MMUs */
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#define MMU_AS(as) (0x2400 + ((as) << 6))
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#define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
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#define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
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#define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */
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#define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */
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#define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */
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#define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
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#define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */
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#define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */
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#define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */
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#define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */
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#define AS_STATUS(as) (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */
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/* Additional Bifrost AS regsiters */
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#define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */
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#define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
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#define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */
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#define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
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/*
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* Begin LPAE MMU TRANSTAB register values
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*/
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#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000
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#define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2
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#define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3
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#define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3
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#define AS_TRANSTAB_LPAE_READ_INNER BIT(2)
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#define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4)
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#define AS_STATUS_AS_ACTIVE 0x01
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#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)
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2021-08-25 02:30:27 +09:00
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#define AS_LOCK_REGION_MIN_SIZE (1ULL << 15)
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2019-06-18 17:16:45 +09:00
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#define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
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#define gpu_read(dev, reg) readl(dev->iomem + reg)
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2018-09-11 04:27:58 +09:00
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#endif
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