License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 23:07:57 +09:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-08-11 02:08:10 +09:00
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#ifndef __ASM_ARM_CPUTYPE_H
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#define __ASM_ARM_CPUTYPE_H
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#include <linux/stringify.h>
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2011-04-14 20:11:42 +09:00
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#include <linux/kernel.h>
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2008-08-11 02:08:10 +09:00
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#define CPUID_ID 0
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#define CPUID_CACHETYPE 1
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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2013-02-22 00:21:34 +09:00
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#define CPUID_MPUIR 4
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2011-08-08 21:21:59 +09:00
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#define CPUID_MPIDR 5
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2013-10-10 01:26:44 +09:00
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#define CPUID_REVIDR 6
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2008-08-11 02:08:10 +09:00
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2013-05-06 18:35:42 +09:00
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#ifdef CONFIG_CPU_V7M
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#define CPUID_EXT_PFR0 0x40
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#define CPUID_EXT_PFR1 0x44
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#define CPUID_EXT_DFR0 0x48
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#define CPUID_EXT_AFR0 0x4c
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#define CPUID_EXT_MMFR0 0x50
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#define CPUID_EXT_MMFR1 0x54
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#define CPUID_EXT_MMFR2 0x58
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#define CPUID_EXT_MMFR3 0x5c
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#define CPUID_EXT_ISAR0 0x60
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#define CPUID_EXT_ISAR1 0x64
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#define CPUID_EXT_ISAR2 0x68
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#define CPUID_EXT_ISAR3 0x6c
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#define CPUID_EXT_ISAR4 0x70
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#define CPUID_EXT_ISAR5 0x74
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#else
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2009-05-30 22:00:14 +09:00
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#define CPUID_EXT_PFR0 "c1, 0"
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#define CPUID_EXT_PFR1 "c1, 1"
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#define CPUID_EXT_DFR0 "c1, 2"
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#define CPUID_EXT_AFR0 "c1, 3"
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#define CPUID_EXT_MMFR0 "c1, 4"
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#define CPUID_EXT_MMFR1 "c1, 5"
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#define CPUID_EXT_MMFR2 "c1, 6"
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#define CPUID_EXT_MMFR3 "c1, 7"
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#define CPUID_EXT_ISAR0 "c2, 0"
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#define CPUID_EXT_ISAR1 "c2, 1"
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#define CPUID_EXT_ISAR2 "c2, 2"
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#define CPUID_EXT_ISAR3 "c2, 3"
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#define CPUID_EXT_ISAR4 "c2, 4"
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#define CPUID_EXT_ISAR5 "c2, 5"
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2013-05-06 18:35:42 +09:00
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#endif
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2009-05-30 22:00:14 +09:00
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2012-11-16 02:30:32 +09:00
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#define MPIDR_SMP_BITMASK (0x3 << 30)
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#define MPIDR_SMP_VALUE (0x2 << 30)
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#define MPIDR_MT_BITMASK (0x1 << 24)
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#define MPIDR_HWID_BITMASK 0xFFFFFF
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2013-06-19 18:40:48 +09:00
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#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
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2012-11-16 02:30:32 +09:00
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#define MPIDR_LEVEL_BITS 8
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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2016-09-12 23:49:21 +09:00
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#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
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2012-11-16 02:30:32 +09:00
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
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2013-03-10 00:49:32 +09:00
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#define ARM_CPU_IMP_ARM 0x41
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2016-08-19 23:15:03 +09:00
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#define ARM_CPU_IMP_DEC 0x44
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2013-03-10 00:49:32 +09:00
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#define ARM_CPU_IMP_INTEL 0x69
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2014-06-25 03:43:15 +09:00
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/* ARM implemented processors */
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#define ARM_CPU_PART_ARM1136 0x4100b360
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#define ARM_CPU_PART_ARM1156 0x4100b560
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#define ARM_CPU_PART_ARM1176 0x4100b760
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#define ARM_CPU_PART_ARM11MPCORE 0x4100b020
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#define ARM_CPU_PART_CORTEX_A8 0x4100c080
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#define ARM_CPU_PART_CORTEX_A9 0x4100c090
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#define ARM_CPU_PART_CORTEX_A5 0x4100c050
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#define ARM_CPU_PART_CORTEX_A7 0x4100c070
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#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
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#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
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#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
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2018-10-16 00:31:55 +09:00
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#define ARM_CPU_PART_CORTEX_A53 0x4100d030
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#define ARM_CPU_PART_CORTEX_A57 0x4100d070
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#define ARM_CPU_PART_CORTEX_A72 0x4100d080
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#define ARM_CPU_PART_CORTEX_A73 0x4100d090
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#define ARM_CPU_PART_CORTEX_A75 0x4100d0a0
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2014-08-15 23:53:14 +09:00
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#define ARM_CPU_PART_MASK 0xff00fff0
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2013-03-10 00:49:32 +09:00
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2018-10-16 00:31:55 +09:00
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/* Broadcom cores */
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#define ARM_CPU_PART_BRAHMA_B15 0x420000f0
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2016-08-19 23:15:03 +09:00
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/* DEC implemented cores */
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#define ARM_CPU_PART_SA1100 0x4400a110
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/* Intel implemented cores */
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#define ARM_CPU_PART_SA1110 0x6900b110
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#define ARM_CPU_REV_SA1110_A0 0
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#define ARM_CPU_REV_SA1110_B0 4
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#define ARM_CPU_REV_SA1110_B1 5
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#define ARM_CPU_REV_SA1110_B2 6
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#define ARM_CPU_REV_SA1110_B4 8
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2013-03-10 00:49:32 +09:00
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#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
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#define ARM_CPU_XSCALE_ARCH_V1 0x2000
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#define ARM_CPU_XSCALE_ARCH_V2 0x4000
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#define ARM_CPU_XSCALE_ARCH_V3 0x6000
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2017-01-06 21:12:47 +09:00
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/* Qualcomm implemented cores */
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#define ARM_CPU_PART_SCORPION 0x510002d0
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2011-01-08 21:05:09 +09:00
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extern unsigned int processor_id;
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2019-02-14 11:10:17 +09:00
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struct proc_info_list *lookup_processor(u32 midr);
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2011-01-08 21:05:09 +09:00
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2008-08-11 02:08:10 +09:00
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#ifdef CONFIG_CPU_CP15
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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2013-01-31 19:08:03 +09:00
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2013-07-30 20:38:45 +09:00
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/*
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* The memory clobber prevents gcc 4.5 from reordering the mrc before
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* any is_smp() tests, which can cause undefined instruction aborts on
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* ARM1136 r0 due to the missing extended CP15 registers.
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*/
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2009-05-30 22:00:14 +09:00
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#define read_cpuid_ext(ext_reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, " ext_reg \
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: "=r" (__val) \
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: \
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2013-07-30 20:38:45 +09:00
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: "memory"); \
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2009-05-30 22:00:14 +09:00
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__val; \
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})
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2008-08-11 02:08:10 +09:00
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2013-05-06 18:35:42 +09:00
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#elif defined(CONFIG_CPU_V7M)
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#include <asm/io.h>
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#include <asm/v7m.h>
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#define read_cpuid(reg) \
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({ \
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WARN_ON_ONCE(1); \
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0; \
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})
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static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
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{
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return readl(BASEADDR_V7M_SCB + offset);
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}
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#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
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2012-12-18 13:06:37 +09:00
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2013-01-31 19:08:03 +09:00
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/*
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* read_cpuid and read_cpuid_ext should only ever be called on machines that
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* have cp15 so warn on other usages.
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*/
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#define read_cpuid(reg) \
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({ \
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WARN_ON_ONCE(1); \
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0; \
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})
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2012-12-18 13:06:37 +09:00
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2013-01-31 19:08:03 +09:00
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#define read_cpuid_ext(reg) read_cpuid(reg)
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2012-12-18 13:06:37 +09:00
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2013-01-31 19:08:03 +09:00
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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#ifdef CONFIG_CPU_CP15
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2008-08-11 02:08:10 +09:00
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(CPUID_ID);
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}
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2016-08-31 01:27:19 +09:00
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(CPUID_CACHETYPE);
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}
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2010-05-22 02:06:41 +09:00
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#elif defined(CONFIG_CPU_V7M)
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
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}
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2016-08-31 01:27:19 +09:00
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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{
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
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}
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2010-05-22 02:06:41 +09:00
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#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
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2013-01-31 19:08:03 +09:00
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return processor_id;
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}
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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2012-12-18 13:06:37 +09:00
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return (read_cpuid_id() & 0xFF000000) >> 24;
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}
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2016-08-19 23:15:03 +09:00
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static inline unsigned int __attribute_const__ read_cpuid_revision(void)
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{
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return read_cpuid_id() & 0x0000000f;
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}
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2014-06-25 03:43:15 +09:00
|
|
|
/*
|
|
|
|
|
* The CPU part number is meaningless without referring to the CPU
|
|
|
|
|
* implementer: implementers are free to define their own part numbers
|
|
|
|
|
* which are permitted to clash with other implementer part numbers.
|
|
|
|
|
*/
|
|
|
|
|
static inline unsigned int __attribute_const__ read_cpuid_part(void)
|
|
|
|
|
{
|
2014-08-15 23:53:14 +09:00
|
|
|
return read_cpuid_id() & ARM_CPU_PART_MASK;
|
2014-06-25 03:43:15 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
|
2012-12-18 13:06:37 +09:00
|
|
|
{
|
|
|
|
|
return read_cpuid_id() & 0xFFF0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
|
|
|
|
|
{
|
2014-06-25 03:43:15 +09:00
|
|
|
return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
|
2012-12-18 13:06:37 +09:00
|
|
|
}
|
|
|
|
|
|
2009-09-16 01:30:37 +09:00
|
|
|
static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
|
|
|
|
|
{
|
|
|
|
|
return read_cpuid(CPUID_TCM);
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-08 21:21:59 +09:00
|
|
|
static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
|
|
|
|
|
{
|
|
|
|
|
return read_cpuid(CPUID_MPIDR);
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-19 23:15:03 +09:00
|
|
|
/* StrongARM-11x0 CPUs */
|
|
|
|
|
#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
|
|
|
|
|
#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
|
|
|
|
|
|
2008-08-11 02:08:10 +09:00
|
|
|
/*
|
|
|
|
|
* Intel's XScale3 core supports some v6 features (supersections, L2)
|
|
|
|
|
* but advertises itself as v5 as it does not support the v6 ISA. For
|
|
|
|
|
* this reason, we need a way to explicitly test for this type of CPU.
|
|
|
|
|
*/
|
|
|
|
|
#ifndef CONFIG_CPU_XSC3
|
|
|
|
|
#define cpu_is_xsc3() 0
|
|
|
|
|
#else
|
|
|
|
|
static inline int cpu_is_xsc3(void)
|
|
|
|
|
{
|
2009-08-21 17:10:41 +09:00
|
|
|
unsigned int id;
|
|
|
|
|
id = read_cpuid_id() & 0xffffe000;
|
|
|
|
|
/* It covers both Intel ID and Marvell ID */
|
|
|
|
|
if ((id == 0x69056000) || (id == 0x56056000))
|
2008-08-11 02:08:10 +09:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
ARM: make xscale iwmmxt code multiplatform aware
In a multiplatform configuration, we may end up building a kernel for
both Marvell PJ1 and an ARMv4 CPU implementation. In that case, the
xscale-cp0 code is built with gcc -march=armv4{,t}, which results in a
build error from the coprocessor instructions.
Since we know this code will only have to run on an actual xscale
processor, we can simply build the entire file for ARMv5TE.
Related to this, we need to handle the iWMMXT initialization sequence
differently during boot, to ensure we don't try to touch xscale
specific registers on other CPUs from the xscale_cp0_init initcall.
cpu_is_xscale() used to be hardcoded to '1' in any configuration that
enables any XScale-compatible core, but this breaks once we can have a
combined kernel with MMP1 and something else.
In this patch, I replace the existing cpu_is_xscale() macro with a new
cpu_is_xscale_family() macro that evaluates true for xscale, xsc3 and
mohawk, which makes the behavior more deterministic.
The two existing users of cpu_is_xscale() are modified accordingly,
but slightly change behavior for kernels that enable CPU_MOHAWK without
also enabling CPU_XSCALE or CPU_XSC3. Previously, these would leave leave
PMD_BIT4 in the page tables untouched, now they clear it as we've always
done for kernels that enable both MOHAWK and the support for the older
CPU types.
Since the previous behavior was inconsistent, I assume it was
unintentional.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-04-15 22:38:39 +09:00
|
|
|
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
|
|
|
|
|
!defined(CONFIG_CPU_MOHAWK)
|
|
|
|
|
#define cpu_is_xscale_family() 0
|
2008-08-11 02:08:10 +09:00
|
|
|
#else
|
ARM: make xscale iwmmxt code multiplatform aware
In a multiplatform configuration, we may end up building a kernel for
both Marvell PJ1 and an ARMv4 CPU implementation. In that case, the
xscale-cp0 code is built with gcc -march=armv4{,t}, which results in a
build error from the coprocessor instructions.
Since we know this code will only have to run on an actual xscale
processor, we can simply build the entire file for ARMv5TE.
Related to this, we need to handle the iWMMXT initialization sequence
differently during boot, to ensure we don't try to touch xscale
specific registers on other CPUs from the xscale_cp0_init initcall.
cpu_is_xscale() used to be hardcoded to '1' in any configuration that
enables any XScale-compatible core, but this breaks once we can have a
combined kernel with MMP1 and something else.
In this patch, I replace the existing cpu_is_xscale() macro with a new
cpu_is_xscale_family() macro that evaluates true for xscale, xsc3 and
mohawk, which makes the behavior more deterministic.
The two existing users of cpu_is_xscale() are modified accordingly,
but slightly change behavior for kernels that enable CPU_MOHAWK without
also enabling CPU_XSCALE or CPU_XSC3. Previously, these would leave leave
PMD_BIT4 in the page tables untouched, now they clear it as we've always
done for kernels that enable both MOHAWK and the support for the older
CPU types.
Since the previous behavior was inconsistent, I assume it was
unintentional.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-04-15 22:38:39 +09:00
|
|
|
static inline int cpu_is_xscale_family(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int id;
|
|
|
|
|
id = read_cpuid_id() & 0xffffe000;
|
|
|
|
|
|
|
|
|
|
switch (id) {
|
|
|
|
|
case 0x69052000: /* Intel XScale 1 */
|
|
|
|
|
case 0x69054000: /* Intel XScale 2 */
|
|
|
|
|
case 0x69056000: /* Intel XScale 3 */
|
|
|
|
|
case 0x56056000: /* Marvell XScale 3 */
|
|
|
|
|
case 0x56158000: /* Marvell Mohawk */
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2008-08-11 02:08:10 +09:00
|
|
|
#endif
|
|
|
|
|
|
2014-04-02 10:47:09 +09:00
|
|
|
/*
|
2014-04-25 06:58:00 +09:00
|
|
|
* Marvell's PJ4 and PJ4B cores are based on V7 version,
|
|
|
|
|
* but require a specical sequence for enabling coprocessors.
|
|
|
|
|
* For this reason, we need a way to distinguish them.
|
2014-04-02 10:47:09 +09:00
|
|
|
*/
|
2014-04-25 06:58:00 +09:00
|
|
|
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
|
2014-04-02 10:47:09 +09:00
|
|
|
static inline int cpu_is_pj4(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int id;
|
|
|
|
|
|
|
|
|
|
id = read_cpuid_id();
|
2014-04-25 06:58:00 +09:00
|
|
|
if ((id & 0xff0fff00) == 0x560f5800)
|
2014-04-02 10:47:09 +09:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2014-04-25 06:58:00 +09:00
|
|
|
#else
|
|
|
|
|
#define cpu_is_pj4() 0
|
2014-04-02 10:47:09 +09:00
|
|
|
#endif
|
2015-03-20 03:03:25 +09:00
|
|
|
|
|
|
|
|
static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
|
|
|
|
|
int field)
|
|
|
|
|
{
|
|
|
|
|
int feature = (features >> field) & 15;
|
|
|
|
|
|
|
|
|
|
/* feature registers are signed values */
|
2016-04-19 20:35:55 +09:00
|
|
|
if (feature > 7)
|
2015-03-20 03:03:25 +09:00
|
|
|
feature -= 16;
|
|
|
|
|
|
|
|
|
|
return feature;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define cpuid_feature_extract(reg, field) \
|
|
|
|
|
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
|
|
|
|
|
|
2008-08-11 02:08:10 +09:00
|
|
|
#endif
|