2018-06-13 03:28:42 +09:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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2015-12-05 07:56:03 +09:00
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/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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2017-04-28 01:47:58 +09:00
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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2018-08-28 15:59:36 +09:00
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* Copyright 2018 NXP
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2015-12-05 07:56:03 +09:00
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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/dts-v1/;
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2016-10-09 15:47:05 +09:00
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#include "fsl-ls1043a.dtsi"
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2015-12-05 07:56:03 +09:00
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/ {
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model = "LS1043A RDB Board";
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2016-05-20 00:11:49 +09:00
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aliases {
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2016-08-30 03:31:12 +09:00
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serial0 = &duart0;
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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2016-05-20 00:11:49 +09:00
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};
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2016-08-30 03:44:44 +09:00
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chosen {
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stdout-path = "serial0:115200n8";
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};
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2015-12-05 07:56:03 +09:00
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};
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&i2c0 {
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status = "okay";
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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eeprom@52 {
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2017-05-23 22:34:42 +09:00
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compatible = "atmel,24c512";
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2015-12-05 07:56:03 +09:00
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reg = <0x52>;
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};
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eeprom@53 {
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2017-05-23 22:34:42 +09:00
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compatible = "atmel,24c512";
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2015-12-05 07:56:03 +09:00
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reg = <0x53>;
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};
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rtc@68 {
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compatible = "pericom,pt7c4338";
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reg = <0x68>;
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};
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arm64: dts: ls1043a: accumulated change for ls1043a boards
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
Author: Peng Ma <peng.ma@nxp.com>
Date: Wed Jul 25 08:53:07 2018 +0000
dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
support
add block-offset to support different virtual block offset for qdma
base on soc;
the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
block,N based on block number of qdma;
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:22:40 2018 +0800
arm64: dts: ls1043a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8
Author: Rajesh Bhagat <rajesh.bhagat@freescale.com>
Date: Wed Jan 27 11:37:25 2016 +0530
arm64: dts: ls1043a: Add configure-gfladj property to USB3 node
Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required
or not
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
Author: Changming Huang <jerry.huang@nxp.com>
Date: Wed Apr 19 12:49:50 2017 +0800
arm/arm64: dts: Add property snps incr burst type adjustment for
INCR burst type for dwc3
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 8632d84e0fe187aa023a24f0dad0040c53e12450
Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Thu Jan 25 11:31:13 2018 +0530
arm64: dts: freescale: ls1043a: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d
Author: Ran Wang <ran.wang_1@nxp.com>
Date: Fri Jan 5 15:14:48 2018 +0800
arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
Enable USB3 HW LPM feature for ls1043a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Jun 13 13:14:26 2017 +0800
arm64: dts: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit f60e39fd51ad702e3a2613faaca40871a4763735
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Aug 22 18:04:02 2017 +0800
arm64: dts: ls1043a: add pcf85263 rtc nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 67c82e3c7b376139d7cee624589bedbc311f8868
Author: jiaheng.fan <jiaheng.fan@nxp.com>
Date: Thu May 11 17:36:33 2017 +0800
arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
commit c6d9c2498ee83669f9853100301edff9a5905caf
Author: Wang Dongsheng <dongsheng.wang@nxp.com>
Date: Fri Apr 21 13:26:07 2017 +0800
arm64: dts: ls1043a: add ftm0 nodes
Add rcpm and ftm0 nodes. The Power Management related features
need these nodes.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
Author: Po Liu <po.liu@nxp.com>
Date: Fri Sep 30 17:11:36 2016 +0800
arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
Some platforms(NXP Layerscape for example) aer/pme interrupts was
not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme
interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes
interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit 4d20ecf029f1255520b30c103e1724c618b981c7
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:51:44 2016 +0800
arm64: dts: ls1043ardb: add ds26522 node
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
commit ca470562646ab058814fc4a1195016fb3266cdf5
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:44:11 2016 +0800
arm64: dts: ls1043ardb: add qe node
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2019-05-03 06:01:01 +09:00
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rtc@51 {
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compatible = "nxp,pcf85263";
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reg = <0x51>;
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};
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2015-12-05 07:56:03 +09:00
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};
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&ifc {
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status = "okay";
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x1 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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nor@0,0 {
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compatible = "cfi-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x0 0x8000000>;
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2018-08-28 15:59:36 +09:00
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big-endian;
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2015-12-05 07:56:03 +09:00
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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cpld: board-control@2,0 {
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compatible = "fsl,ls1043ardb-cpld";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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2016-03-02 14:52:15 +09:00
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
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reg = <0>;
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spi-max-frequency = <1000000>; /* input clock */
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};
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arm64: dts: ls1043a: accumulated change for ls1043a boards
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
Author: Peng Ma <peng.ma@nxp.com>
Date: Wed Jul 25 08:53:07 2018 +0000
dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
support
add block-offset to support different virtual block offset for qdma
base on soc;
the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
block,N based on block number of qdma;
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:22:40 2018 +0800
arm64: dts: ls1043a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8
Author: Rajesh Bhagat <rajesh.bhagat@freescale.com>
Date: Wed Jan 27 11:37:25 2016 +0530
arm64: dts: ls1043a: Add configure-gfladj property to USB3 node
Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required
or not
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
Author: Changming Huang <jerry.huang@nxp.com>
Date: Wed Apr 19 12:49:50 2017 +0800
arm/arm64: dts: Add property snps incr burst type adjustment for
INCR burst type for dwc3
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 8632d84e0fe187aa023a24f0dad0040c53e12450
Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Thu Jan 25 11:31:13 2018 +0530
arm64: dts: freescale: ls1043a: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d
Author: Ran Wang <ran.wang_1@nxp.com>
Date: Fri Jan 5 15:14:48 2018 +0800
arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
Enable USB3 HW LPM feature for ls1043a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Jun 13 13:14:26 2017 +0800
arm64: dts: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit f60e39fd51ad702e3a2613faaca40871a4763735
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Aug 22 18:04:02 2017 +0800
arm64: dts: ls1043a: add pcf85263 rtc nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 67c82e3c7b376139d7cee624589bedbc311f8868
Author: jiaheng.fan <jiaheng.fan@nxp.com>
Date: Thu May 11 17:36:33 2017 +0800
arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
commit c6d9c2498ee83669f9853100301edff9a5905caf
Author: Wang Dongsheng <dongsheng.wang@nxp.com>
Date: Fri Apr 21 13:26:07 2017 +0800
arm64: dts: ls1043a: add ftm0 nodes
Add rcpm and ftm0 nodes. The Power Management related features
need these nodes.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
Author: Po Liu <po.liu@nxp.com>
Date: Fri Sep 30 17:11:36 2016 +0800
arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
Some platforms(NXP Layerscape for example) aer/pme interrupts was
not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme
interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes
interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit 4d20ecf029f1255520b30c103e1724c618b981c7
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:51:44 2016 +0800
arm64: dts: ls1043ardb: add ds26522 node
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
commit ca470562646ab058814fc4a1195016fb3266cdf5
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:44:11 2016 +0800
arm64: dts: ls1043ardb: add qe node
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2019-05-03 06:01:01 +09:00
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slic@2 {
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compatible = "maxim,ds26522";
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reg = <2>;
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spi-max-frequency = <2000000>;
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fsl,spi-cs-sck-delay = <100>;
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fsl,spi-sck-cs-delay = <50>;
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};
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slic@3 {
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compatible = "maxim,ds26522";
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reg = <3>;
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spi-max-frequency = <2000000>;
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fsl,spi-cs-sck-delay = <100>;
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fsl,spi-sck-cs-delay = <50>;
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};
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};
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&uqe {
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ucc_hdlc: ucc@2000 {
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compatible = "fsl,ucc-hdlc";
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rx-clock-name = "clk8";
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tx-clock-name = "clk9";
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fsl,rx-sync-clock = "rsync_pin";
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fsl,tx-sync-clock = "tsync_pin";
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fsl,tx-timeslot-mask = <0xfffffffe>;
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fsl,rx-timeslot-mask = <0xfffffffe>;
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fsl,tdm-framer-type = "e1";
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fsl,tdm-id = <0>;
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fsl,siram-entry-id = <0>;
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fsl,tdm-interface;
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};
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2016-03-02 14:52:15 +09:00
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};
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2015-12-05 07:56:03 +09:00
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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2017-05-16 21:07:22 +09:00
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#include "fsl-ls1043-post.dtsi"
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&fman0 {
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ethernet@e0000 {
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phy-handle = <&qsgmii_phy1>;
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phy-connection-type = "qsgmii";
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};
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ethernet@e2000 {
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phy-handle = <&qsgmii_phy2>;
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phy-connection-type = "qsgmii";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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2020-03-16 21:05:57 +09:00
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phy-connection-type = "rgmii-id";
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2017-05-16 21:07:22 +09:00
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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2020-03-16 21:05:57 +09:00
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phy-connection-type = "rgmii-id";
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2017-05-16 21:07:22 +09:00
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};
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ethernet@e8000 {
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phy-handle = <&qsgmii_phy3>;
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phy-connection-type = "qsgmii";
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};
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ethernet@ea000 {
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phy-handle = <&qsgmii_phy4>;
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phy-connection-type = "qsgmii";
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};
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ethernet@f0000 { /* 10GEC1 */
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phy-handle = <&aqr105_phy>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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qsgmii_phy1: ethernet-phy@4 {
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reg = <0x4>;
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|
|
|
};
|
|
|
|
|
|
|
|
qsgmii_phy2: ethernet-phy@5 {
|
|
|
|
reg = <0x5>;
|
|
|
|
};
|
|
|
|
|
|
|
|
qsgmii_phy3: ethernet-phy@6 {
|
|
|
|
reg = <0x6>;
|
|
|
|
};
|
|
|
|
|
|
|
|
qsgmii_phy4: ethernet-phy@7 {
|
|
|
|
reg = <0x7>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
mdio@fd000 {
|
|
|
|
aqr105_phy: ethernet-phy@1 {
|
|
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
|
|
interrupts = <0 132 4>;
|
|
|
|
reg = <0x1>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|