2019-06-04 17:11:33 +09:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
2011-08-10 00:15:17 +09:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
|
|
|
*/
|
|
|
|
|
2018-01-12 09:04:03 +09:00
|
|
|
#include <dt-bindings/bus/ti-sysc.h>
|
|
|
|
#include <dt-bindings/clock/omap4.h>
|
2013-05-31 21:32:56 +09:00
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
2013-05-31 21:32:57 +09:00
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
2013-05-31 21:32:59 +09:00
|
|
|
#include <dt-bindings/pinctrl/omap.h>
|
2017-12-09 00:17:27 +09:00
|
|
|
#include <dt-bindings/clock/omap4.h>
|
2011-08-10 00:15:17 +09:00
|
|
|
|
|
|
|
/ {
|
|
|
|
compatible = "ti,omap4430", "ti,omap4";
|
2015-03-12 00:43:49 +09:00
|
|
|
interrupt-parent = <&wakeupgen>;
|
2016-08-31 19:35:19 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
2016-12-19 23:44:35 +09:00
|
|
|
chosen { };
|
2011-08-10 00:15:17 +09:00
|
|
|
|
|
|
|
aliases {
|
2013-10-17 05:21:03 +09:00
|
|
|
i2c0 = &i2c1;
|
|
|
|
i2c1 = &i2c2;
|
|
|
|
i2c2 = &i2c3;
|
|
|
|
i2c3 = &i2c4;
|
2011-12-14 20:55:46 +09:00
|
|
|
serial0 = &uart1;
|
|
|
|
serial1 = &uart2;
|
|
|
|
serial2 = &uart3;
|
|
|
|
serial3 = &uart4;
|
2011-08-10 00:15:17 +09:00
|
|
|
};
|
|
|
|
|
2011-08-16 18:49:08 +09:00
|
|
|
cpus {
|
2013-04-19 02:35:59 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
2011-08-16 18:49:08 +09:00
|
|
|
cpu@0 {
|
|
|
|
compatible = "arm,cortex-a9";
|
2013-04-19 02:35:59 +09:00
|
|
|
device_type = "cpu";
|
2012-07-04 21:27:34 +09:00
|
|
|
next-level-cache = <&L2>;
|
2013-04-19 02:35:59 +09:00
|
|
|
reg = <0x0>;
|
2014-01-30 03:19:17 +09:00
|
|
|
|
|
|
|
clocks = <&dpll_mpu_ck>;
|
|
|
|
clock-names = "cpu";
|
|
|
|
|
|
|
|
clock-latency = <300000>; /* From omap-cpufreq driver */
|
2011-08-16 18:49:08 +09:00
|
|
|
};
|
|
|
|
cpu@1 {
|
|
|
|
compatible = "arm,cortex-a9";
|
2013-04-19 02:35:59 +09:00
|
|
|
device_type = "cpu";
|
2012-07-04 21:27:34 +09:00
|
|
|
next-level-cache = <&L2>;
|
2013-04-19 02:35:59 +09:00
|
|
|
reg = <0x1>;
|
2011-08-16 18:49:08 +09:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-08-31 00:19:38 +09:00
|
|
|
/*
|
|
|
|
* Note that 4430 needs cross trigger interface (CTI) supported
|
|
|
|
* before we can configure the interrupts. This means sampling
|
|
|
|
* events are not supported for pmu. Note that 4460 does not use
|
|
|
|
* CTI, see also 4460.dtsi.
|
|
|
|
*/
|
|
|
|
pmu {
|
|
|
|
compatible = "arm,cortex-a9-pmu";
|
|
|
|
ti,hwmods = "debugss";
|
|
|
|
};
|
|
|
|
|
2012-09-04 00:56:32 +09:00
|
|
|
gic: interrupt-controller@48241000 {
|
|
|
|
compatible = "arm,cortex-a9-gic";
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
reg = <0x48241000 0x1000>,
|
|
|
|
<0x48240100 0x0100>;
|
2015-03-12 00:43:49 +09:00
|
|
|
interrupt-parent = <&gic>;
|
2012-09-04 00:56:32 +09:00
|
|
|
};
|
|
|
|
|
2012-07-04 21:27:34 +09:00
|
|
|
L2: l2-cache-controller@48242000 {
|
|
|
|
compatible = "arm,pl310-cache";
|
|
|
|
reg = <0x48242000 0x1000>;
|
|
|
|
cache-unified;
|
|
|
|
cache-level = <2>;
|
|
|
|
};
|
|
|
|
|
2013-07-22 19:52:36 +09:00
|
|
|
local-timer@48240600 {
|
2012-07-04 22:02:32 +09:00
|
|
|
compatible = "arm,cortex-a9-twd-timer";
|
2014-04-08 05:05:39 +09:00
|
|
|
clocks = <&mpu_periphclk>;
|
2012-07-04 22:02:32 +09:00
|
|
|
reg = <0x48240600 0x20>;
|
2016-03-17 23:19:06 +09:00
|
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
|
2015-03-12 00:43:49 +09:00
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
};
|
|
|
|
|
|
|
|
wakeupgen: interrupt-controller@48281000 {
|
|
|
|
compatible = "ti,omap4-wugen-mpu";
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
reg = <0x48281000 0x1000>;
|
|
|
|
interrupt-parent = <&gic>;
|
2012-07-04 22:02:32 +09:00
|
|
|
};
|
|
|
|
|
2011-08-10 00:15:17 +09:00
|
|
|
/*
|
2014-03-28 19:11:37 +09:00
|
|
|
* The soc node represents the soc top level view. It is used for IPs
|
2011-08-10 00:15:17 +09:00
|
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
|
|
|
*/
|
|
|
|
soc {
|
|
|
|
compatible = "ti,omap-infra";
|
2011-08-16 18:49:08 +09:00
|
|
|
mpu {
|
|
|
|
compatible = "ti,omap4-mpu";
|
|
|
|
ti,hwmods = "mpu";
|
2014-09-11 01:04:04 +09:00
|
|
|
sram = <&ocmcram>;
|
2011-08-16 18:49:08 +09:00
|
|
|
};
|
|
|
|
|
|
|
|
dsp {
|
|
|
|
compatible = "ti,omap3-c64";
|
|
|
|
ti,hwmods = "dsp";
|
|
|
|
};
|
|
|
|
|
|
|
|
iva {
|
|
|
|
compatible = "ti,ivahd";
|
|
|
|
ti,hwmods = "iva";
|
|
|
|
};
|
2011-08-10 00:15:17 +09:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: Use a flat representation of the OMAP4 interconnect.
|
|
|
|
* The real OMAP interconnect network is quite complex.
|
2014-03-28 19:11:39 +09:00
|
|
|
* Since it will not bring real advantage to represent that in DT for
|
2011-08-10 00:15:17 +09:00
|
|
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
|
|
|
* hierarchy.
|
|
|
|
*/
|
|
|
|
ocp {
|
2011-08-12 20:48:47 +09:00
|
|
|
compatible = "ti,omap4-l3-noc", "simple-bus";
|
2011-08-10 00:15:17 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
2011-08-12 20:48:47 +09:00
|
|
|
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
2013-02-26 21:06:14 +09:00
|
|
|
reg = <0x44000000 0x1000>,
|
|
|
|
<0x44800000 0x2000>,
|
|
|
|
<0x45000000 0x1000>;
|
2013-05-31 21:32:57 +09:00
|
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
2011-08-10 00:15:17 +09:00
|
|
|
|
2018-07-06 15:19:37 +09:00
|
|
|
l4_wkup: interconnect@4a300000 {
|
|
|
|
};
|
2017-08-31 00:19:39 +09:00
|
|
|
|
2018-07-06 15:19:37 +09:00
|
|
|
l4_cfg: interconnect@4a000000 {
|
|
|
|
};
|
2017-08-31 00:19:39 +09:00
|
|
|
|
2018-07-06 15:19:37 +09:00
|
|
|
l4_per: interconnect@48000000 {
|
2014-02-19 23:56:40 +09:00
|
|
|
};
|
|
|
|
|
2019-04-10 01:00:53 +09:00
|
|
|
l4_abe: interconnect@40100000 {
|
|
|
|
};
|
|
|
|
|
2014-09-11 01:04:03 +09:00
|
|
|
ocmcram: ocmcram@40304000 {
|
|
|
|
compatible = "mmio-sram";
|
|
|
|
reg = <0x40304000 0xa000>; /* 40k */
|
|
|
|
};
|
|
|
|
|
2013-02-23 06:33:31 +09:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
compatible = "ti,omap4430-gpmc";
|
|
|
|
reg = <0x50000000 0x1000>;
|
|
|
|
#address-cells = <2>;
|
|
|
|
#size-cells = <1>;
|
2013-05-31 21:32:57 +09:00
|
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
2015-10-16 02:37:27 +09:00
|
|
|
dmas = <&sdma 4>;
|
|
|
|
dma-names = "rxtx";
|
2013-02-23 06:33:31 +09:00
|
|
|
gpmc,num-cs = <8>;
|
|
|
|
gpmc,num-waitpins = <4>;
|
|
|
|
ti,hwmods = "gpmc";
|
2013-10-15 16:07:50 +09:00
|
|
|
ti,no-idle-on-init;
|
2014-02-26 19:38:09 +09:00
|
|
|
clocks = <&l3_div_ck>;
|
|
|
|
clock-names = "fck";
|
2016-04-07 19:25:29 +09:00
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
2013-02-23 06:33:31 +09:00
|
|
|
};
|
|
|
|
|
2014-03-06 09:24:18 +09:00
|
|
|
mmu_dsp: mmu@4a066000 {
|
|
|
|
compatible = "ti,omap4-iommu";
|
|
|
|
reg = <0x4a066000 0x100>;
|
|
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ti,hwmods = "mmu_dsp";
|
2015-07-11 02:28:55 +09:00
|
|
|
#iommu-cells = <0>;
|
2014-03-06 09:24:18 +09:00
|
|
|
};
|
|
|
|
|
2017-10-11 06:14:50 +09:00
|
|
|
target-module@52000000 {
|
2017-12-14 09:36:47 +09:00
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
2017-10-11 06:14:50 +09:00
|
|
|
ti,hwmods = "iss";
|
|
|
|
reg = <0x52000000 0x4>,
|
|
|
|
<0x52000010 0x4>;
|
|
|
|
reg-names = "rev", "sysc";
|
2018-01-12 09:04:03 +09:00
|
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
ti,sysc-delay-us = <2>;
|
|
|
|
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
|
|
|
|
clock-names = "fck";
|
2017-10-11 06:14:50 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0x52000000 0x1000000>;
|
|
|
|
|
|
|
|
/* No child device binding, driver in staging */
|
|
|
|
};
|
|
|
|
|
2014-03-06 09:24:18 +09:00
|
|
|
mmu_ipu: mmu@55082000 {
|
|
|
|
compatible = "ti,omap4-iommu";
|
|
|
|
reg = <0x55082000 0x100>;
|
|
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ti,hwmods = "mmu_ipu";
|
2015-07-11 02:28:55 +09:00
|
|
|
#iommu-cells = <0>;
|
2014-03-06 09:24:18 +09:00
|
|
|
ti,iommu-bus-err-back;
|
|
|
|
};
|
2017-10-11 06:14:50 +09:00
|
|
|
target-module@4012c000 {
|
2017-12-14 09:36:47 +09:00
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
2017-10-11 06:14:50 +09:00
|
|
|
ti,hwmods = "slimbus1";
|
|
|
|
reg = <0x4012c000 0x4>,
|
|
|
|
<0x4012c010 0x4>;
|
|
|
|
reg-names = "rev", "sysc";
|
2018-01-12 09:04:03 +09:00
|
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
|
|
|
|
clock-names = "fck";
|
2017-10-11 06:14:50 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
|
|
|
|
<0x4902c000 0x4902c000 0x1000>; /* L3 */
|
|
|
|
|
|
|
|
/* No child device binding or driver in mainline */
|
|
|
|
};
|
|
|
|
|
2013-12-17 19:02:21 +09:00
|
|
|
dmm@4e000000 {
|
|
|
|
compatible = "ti,omap4-dmm";
|
|
|
|
reg = <0x4e000000 0x800>;
|
|
|
|
interrupts = <0 113 0x4>;
|
|
|
|
ti,hwmods = "dmm";
|
|
|
|
};
|
|
|
|
|
2012-01-21 00:05:26 +09:00
|
|
|
emif1: emif@4c000000 {
|
|
|
|
compatible = "ti,emif-4d";
|
2012-09-05 18:38:23 +09:00
|
|
|
reg = <0x4c000000 0x100>;
|
2013-05-31 21:32:57 +09:00
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
2012-01-21 00:05:26 +09:00
|
|
|
ti,hwmods = "emif1";
|
2013-10-15 16:07:50 +09:00
|
|
|
ti,no-idle-on-init;
|
2012-01-21 00:05:26 +09:00
|
|
|
phy-type = <1>;
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
};
|
|
|
|
|
|
|
|
emif2: emif@4d000000 {
|
|
|
|
compatible = "ti,emif-4d";
|
2012-09-05 18:38:23 +09:00
|
|
|
reg = <0x4d000000 0x100>;
|
2013-05-31 21:32:57 +09:00
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
2012-01-21 00:05:26 +09:00
|
|
|
ti,hwmods = "emif2";
|
2013-10-15 16:07:50 +09:00
|
|
|
ti,no-idle-on-init;
|
2012-01-21 00:05:26 +09:00
|
|
|
phy-type = <1>;
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
};
|
2012-10-02 10:46:13 +09:00
|
|
|
|
2017-06-13 18:28:43 +09:00
|
|
|
aes1: aes@4b501000 {
|
2013-07-12 08:20:05 +09:00
|
|
|
compatible = "ti,omap4-aes";
|
2017-06-13 18:28:43 +09:00
|
|
|
ti,hwmods = "aes1";
|
2013-07-12 08:20:05 +09:00
|
|
|
reg = <0x4b501000 0xa0>;
|
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dmas = <&sdma 111>, <&sdma 110>;
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
};
|
2013-09-25 05:23:33 +09:00
|
|
|
|
2017-06-13 22:45:48 +09:00
|
|
|
aes2: aes@4b701000 {
|
|
|
|
compatible = "ti,omap4-aes";
|
|
|
|
ti,hwmods = "aes2";
|
|
|
|
reg = <0x4b701000 0xa0>;
|
|
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dmas = <&sdma 114>, <&sdma 113>;
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
};
|
|
|
|
|
2013-09-25 05:23:33 +09:00
|
|
|
des: des@480a5000 {
|
|
|
|
compatible = "ti,omap4-des";
|
|
|
|
ti,hwmods = "des";
|
|
|
|
reg = <0x480a5000 0xa0>;
|
|
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dmas = <&sdma 117>, <&sdma 116>;
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
};
|
2014-03-03 23:50:22 +09:00
|
|
|
|
2017-06-13 22:45:49 +09:00
|
|
|
sham: sham@4b100000 {
|
|
|
|
compatible = "ti,omap4-sham";
|
|
|
|
ti,hwmods = "sham";
|
|
|
|
reg = <0x4b100000 0x300>;
|
|
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dmas = <&sdma 119>;
|
|
|
|
dma-names = "rx";
|
|
|
|
};
|
|
|
|
|
2014-03-03 23:50:22 +09:00
|
|
|
abb_mpu: regulator-abb-mpu {
|
|
|
|
compatible = "ti,abb-v2";
|
|
|
|
regulator-name = "abb_mpu";
|
|
|
|
#address-cells = <0>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
ti,tranxdone-status-mask = <0x80>;
|
|
|
|
clocks = <&sys_clkin_ck>;
|
|
|
|
ti,settling-time = <50>;
|
|
|
|
ti,clock-cycles = <16>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
abb_iva: regulator-abb-iva {
|
|
|
|
compatible = "ti,abb-v2";
|
|
|
|
regulator-name = "abb_iva";
|
|
|
|
#address-cells = <0>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
ti,tranxdone-status-mask = <0x80000000>;
|
|
|
|
clocks = <&sys_clkin_ck>;
|
|
|
|
ti,settling-time = <50>;
|
|
|
|
ti,clock-cycles = <16>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2012-08-21 21:34:50 +09:00
|
|
|
|
2017-10-11 06:14:50 +09:00
|
|
|
target-module@56000000 {
|
2017-12-14 09:36:47 +09:00
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
2019-11-25 02:43:16 +09:00
|
|
|
reg = <0x5600fe00 0x4>,
|
|
|
|
<0x5600fe10 0x4>;
|
2017-10-11 06:14:50 +09:00
|
|
|
reg-names = "rev", "sysc";
|
2018-01-12 09:04:03 +09:00
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
|
|
|
|
clock-names = "fck";
|
2017-10-11 06:14:50 +09:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0x56000000 0x2000000>;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Closed source PowerVR driver, no child device
|
|
|
|
* binding or driver in mainline
|
|
|
|
*/
|
|
|
|
};
|
|
|
|
|
2012-08-21 21:34:50 +09:00
|
|
|
dss: dss@58000000 {
|
|
|
|
compatible = "ti,omap4-dss";
|
|
|
|
reg = <0x58000000 0x80>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_core";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
dispc@58001000 {
|
|
|
|
compatible = "ti,omap4-dispc";
|
|
|
|
reg = <0x58001000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ti,hwmods = "dss_dispc";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck";
|
|
|
|
};
|
|
|
|
|
|
|
|
rfbi: encoder@58002000 {
|
|
|
|
compatible = "ti,omap4-rfbi";
|
|
|
|
reg = <0x58002000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_rfbi";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck", "ick";
|
|
|
|
};
|
|
|
|
|
|
|
|
venc: encoder@58003000 {
|
|
|
|
compatible = "ti,omap4-venc";
|
|
|
|
reg = <0x58003000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_venc";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck";
|
|
|
|
};
|
|
|
|
|
|
|
|
dsi1: encoder@58004000 {
|
|
|
|
compatible = "ti,omap4-dsi";
|
|
|
|
reg = <0x58004000 0x200>,
|
|
|
|
<0x58004200 0x40>,
|
|
|
|
<0x58004300 0x20>;
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_dsi1";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
};
|
|
|
|
|
|
|
|
dsi2: encoder@58005000 {
|
|
|
|
compatible = "ti,omap4-dsi";
|
|
|
|
reg = <0x58005000 0x200>,
|
|
|
|
<0x58005200 0x40>,
|
|
|
|
<0x58005300 0x20>;
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_dsi2";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
};
|
|
|
|
|
|
|
|
hdmi: encoder@58006000 {
|
|
|
|
compatible = "ti,omap4-hdmi";
|
|
|
|
reg = <0x58006000 0x200>,
|
|
|
|
<0x58006200 0x100>,
|
|
|
|
<0x58006300 0x100>,
|
|
|
|
<0x58006400 0x1000>;
|
|
|
|
reg-names = "wp", "pll", "phy", "core";
|
|
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
status = "disabled";
|
|
|
|
ti,hwmods = "dss_hdmi";
|
2017-12-09 00:17:27 +09:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
2012-08-21 21:34:50 +09:00
|
|
|
clock-names = "fck", "sys_clk";
|
2014-05-12 18:12:24 +09:00
|
|
|
dmas = <&sdma 76>;
|
|
|
|
dma-names = "audio_tx";
|
2012-08-21 21:34:50 +09:00
|
|
|
};
|
|
|
|
};
|
2011-08-10 00:15:17 +09:00
|
|
|
};
|
|
|
|
};
|
2013-07-18 18:42:02 +09:00
|
|
|
|
2018-07-06 15:19:37 +09:00
|
|
|
#include "omap4-l4.dtsi"
|
2019-04-10 01:00:53 +09:00
|
|
|
#include "omap4-l4-abe.dtsi"
|
2017-12-09 00:17:27 +09:00
|
|
|
#include "omap44xx-clocks.dtsi"
|