mirror of
https://github.com/brain-hackers/lab
synced 2024-11-15 06:38:01 +09:00
333 lines
8.6 KiB
C
333 lines
8.6 KiB
C
#include "common.h"
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#include "pcc.h"
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#include "imx-regs.h"
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#include "fsl_lpuart.h"
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#define US1_TDRE (1 << 7)
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#define US1_RDRF (1 << 5)
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#define US1_OR (1 << 3)
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#define UC2_TE (1 << 3)
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#define UC2_RE (1 << 2)
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#define CFIFO_TXFLUSH (1 << 7)
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#define CFIFO_RXFLUSH (1 << 6)
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#define SFIFO_RXOF (1 << 2)
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#define SFIFO_RXUF (1 << 0)
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#define STAT_LBKDIF (1 << 31)
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#define STAT_RXEDGIF (1 << 30)
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#define STAT_TDRE (1 << 23)
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#define STAT_RDRF (1 << 21)
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#define STAT_IDLE (1 << 20)
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#define STAT_OR (1 << 19)
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#define STAT_NF (1 << 18)
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#define STAT_FE (1 << 17)
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#define STAT_PF (1 << 16)
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#define STAT_MA1F (1 << 15)
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#define STAT_MA2F (1 << 14)
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#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
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STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
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#define CTRL_ORIE (1 << 27)
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#define CTRL_NEIE (1 << 26)
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#define CTRL_FEIE (1 << 25)
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#define CTRL_PEIE (1 << 24)
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#define CTRL_TIE (1 << 23)
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#define CTRL_TCIE (1 << 22)
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#define CTRL_RIE (1 << 21)
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#define CTRL_ILIE (1 << 20)
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#define CTRL_TE (1 << 19)
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#define CTRL_RE (1 << 18)
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#define CTRL_MA1IE (1 << 15)
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#define CTRL_MA2IE (1 << 14)
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#define FIFO_TXOFE (1 << 9)
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#define FIFO_RXUFE (1 << 8)
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#define FIFO_TXFE (1 << 7)
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#define FIFO_RXFE (1 << 3)
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static struct lpuart_fsl_reg32* regs[] = {
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(struct lpuart_fsl_reg32*)0x4103A000,
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(struct lpuart_fsl_reg32*)0x4103B000,
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(struct lpuart_fsl_reg32*)0x410AB000,
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(struct lpuart_fsl_reg32*)0x410AC000,
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(struct lpuart_fsl_reg32*)0x402D0000,
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(struct lpuart_fsl_reg32*)0x402E0000,
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(struct lpuart_fsl_reg32*)0x40A60000,
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(struct lpuart_fsl_reg32*)0x40A70000,
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};
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static void lpuart_read32(u32 *addr, u32 *val) {
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*(u32 *)val = readl(addr);
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}
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static void lpuart_write32(u32 *addr, u32 val) {
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writel(val, addr);
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}
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// clk
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static enum scg_clk pcc_clksrc[2][7] = {
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{
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SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_DDR_CLK,
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SCG_APLL_PFD2_CLK,
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SCG_APLL_PFD1_CLK,
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SCG_APLL_PFD0_CLK,
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USB_PLL_OUT,
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},
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{
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SCG_SOSC_DIV2_CLK,
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MIPI_PLL_OUT,
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SCG_FIRC_DIV2_CLK,
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SCG_ROSC_CLK,
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SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_APLL_PFD3_CLK,
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},
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};
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static struct pcc_entry pcc_arrays[] = {
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{PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
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{PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
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};
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int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
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{
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u32 reg, val, clksrc_type;
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clksrc_type = pcc_arrays[clk].clksrc;
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if (clksrc_type >= CLKSRC_NO_PCS) {
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return 1;
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}
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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if (!(val & PCC_PR_MASK)) {
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return 2;
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}
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val &= PCC_PCS_MASK;
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val = (val >> PCC_PCS_OFFSET);
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if (!val) {
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return 3;
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}
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*src = pcc_clksrc[clksrc_type][val - 1];
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return 0;
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}
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u32 pcc_clock_get_rate(enum pcc_clk clk)
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{
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u32 reg, val, rate, frac, div;
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enum scg_clk parent;
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int ret;
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ret = pcc_clock_get_clksrc(clk, &parent);
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if (ret)
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return 0;
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rate = scg_clk_get_rate(parent);
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if (pcc_arrays[clk].div == PCC_HAS_DIV) {
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reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
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val = readl(reg);
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frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
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div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
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rate = rate * (frac + 1) / (div + 1);
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}
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return rate;
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}
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static void setbrg(struct lpuart_fsl_reg32* reg, int baudrate)
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{
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u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
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u32 clk = pcc_clock_get_rate(PER_CLK_LPUART4);
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baud_diff = baudrate;
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osr = 0;
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sbr = 0;
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for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
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tmp_sbr = (clk / (baudrate * tmp_osr));
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if (tmp_sbr == 0)
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tmp_sbr = 1;
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/*calculate difference in actual buad w/ current values */
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tmp_diff = (clk / (tmp_osr * tmp_sbr));
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tmp_diff = tmp_diff - baudrate;
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/* select best values between sbr and sbr+1 */
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if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
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tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
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tmp_sbr++;
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}
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if (tmp_diff <= baud_diff) {
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baud_diff = tmp_diff;
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osr = tmp_osr;
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sbr = tmp_sbr;
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}
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}
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tmp = readl(®->baud);
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if ((osr > 3) && (osr < 8))
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tmp |= LPUART_BAUD_BOTHEDGE_MASK;
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tmp &= ~LPUART_BAUD_OSR_MASK;
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tmp |= LPUART_BAUD_OSR(osr-1);
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tmp &= ~LPUART_BAUD_SBR_MASK;
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tmp |= LPUART_BAUD_SBR(sbr);
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/* explicitly disable 10 bit mode & set 1 stop bit */
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tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
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writel(tmp, ®->baud);
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}
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static void serial_putc(struct lpuart_fsl_reg32* reg, const char c) {
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u32 stat;
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while (1) {
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lpuart_read32(®->stat, &stat);
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if (stat & STAT_TDRE) {
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break;
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}
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}
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lpuart_write32(®->data, c);
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}
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struct iomux {
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u16 buf;
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u8 mode;
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u8 pull;
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};
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void iomux() {
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u32 pcc_u4;
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struct iomux imu4;
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pcc_u4 = readl(0x403f00b4);
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pcc_u4 |= (1 << 30);
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writel(pcc_u4, 0x403f00b4);
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imu4.buf = 0b0011; // PTC2 U4 TX
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imu4.mode = 0b0100; // PTC2 U4 TX
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imu4.pull = 0b11; // PTC2 U4 TX
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writel(*((u32 *)&imu4), (u32 *)0x40ac0008);
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//writel(0x0000000a, 0x400f0004);
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//writel(0x000fffff, 0x400f0004);
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//writel(0x00000fff, 0x400f0044);
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//writel(0x0000ffff, 0x400f0084);
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//writel(0x000fffff, 0x400f00c4);
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}
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void main() {
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u32 ctrl, baud, i;
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writel(0x00000004, 0x400f0004);
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iomux();
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lpuart_write32(®s[4]->global, 0); // De-assert reset:w
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lpuart_read32(®s[4]->baud, &baud);
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baud &= ~(1 << 15); // LBKDIE
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baud &= ~(1 << 14); // RXEDGIE
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lpuart_write32(®s[4]->baud, baud);
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lpuart_read32(®s[4]->ctrl, &ctrl);
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ctrl &= ~CTRL_ORIE;
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ctrl &= ~CTRL_NEIE;
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ctrl &= ~CTRL_FEIE;
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ctrl &= ~CTRL_PEIE;
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ctrl &= ~CTRL_TIE;
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ctrl &= ~CTRL_TCIE;
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ctrl &= ~CTRL_RIE;
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ctrl &= ~CTRL_ILIE;
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ctrl &= ~CTRL_MA1IE;
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ctrl &= ~CTRL_MA2IE;
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ctrl &= ~CTRL_RE;
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ctrl &= ~CTRL_TE;
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lpuart_write32(®s[4]->ctrl, ctrl);
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lpuart_write32(®s[4]->modir, 0);
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lpuart_write32(®s[4]->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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lpuart_write32(®s[4]->match, 0);
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setbrg(regs[4], 115200);
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ctrl |= CTRL_RE;
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ctrl |= CTRL_TE;
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lpuart_write32(®s[4]->ctrl, ctrl);
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// putc
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while (1) {
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for (i=0; i<8; i++) {
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serial_putc(regs[4], 'Y');
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serial_putc(regs[4], '\n');
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}
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}
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asm volatile(
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"mov pc, lr\n"
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);
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}
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