Compare commits

...

4 Commits

Author SHA1 Message Date
Takumi Sueda 7c2200e371 Update injector impl 2021-06-17 01:56:48 +09:00
Takumi Sueda 40ab815357 Add injector/uboot.bin target 2021-06-17 01:56:48 +09:00
Takumi Sueda 63b15a9455
Merge pull request #1 from brain-hackers/lcdbench
Add lcdbench
2021-06-01 02:32:18 +09:00
Takumi Sueda 4cae220a92 Add lcdbench 2021-06-01 02:31:53 +09:00
5 changed files with 120 additions and 7 deletions

View File

@ -6,6 +6,7 @@
- [read_keys_SH3.py](read_keys_SH3.py) Scan key matrix and return key name(deprecated)
- [read_keys_SH3.c](read_keys_SH3.c) Scan key matrix and return key name rewritten with C. nice performance
- [x1](x1) Executable to analyze `[JHSBA]1` gen
- [lcdbench](lcdbench) Benchmark fb0 fill and show results
### License

11
lcdbench/Makefile Normal file
View File

@ -0,0 +1,11 @@
CC?=arm-linux-gnueabi-gcc
all: lcdbench
.PHONY:
clean:
rm -f lcdbench
lcdbench: lcdbench.c
$(CC) $< -o $@

63
lcdbench/lcdbench.c Normal file
View File

@ -0,0 +1,63 @@
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <time.h>
const int width = 800;
const int height = 480;
// 1 loop = 2 draws
// 30 loop = 60 draws = 1 sec (60 fps)
const int nloop = 30 * 3;
struct timespec diff(struct timespec start, struct timespec end);
int main(void) {
FILE *f;
uint16_t buf1[width * height]; //RGB565
uint16_t buf2[width * height];
struct timespec ts1, ts2, d;
int i, j;
float elapsed;
for (i = 0; i < height; i++) {
for (j = 0; j < width; j++) {
buf1[i * width + j] = (i << 8) + j;
buf2[i * width + j] = ~((i << 8) + j);
}
}
f = fopen("/dev/fb0", "w");
if (f == NULL) {
printf("Could not open /dev/fb0\n");
return 1;
}
clock_gettime(CLOCK_MONOTONIC, &ts1);
for (j = 0; j < nloop; j++) {
fwrite(buf1, sizeof(buf1), 1, f);
fseek(f, 0, SEEK_SET);
fwrite(buf2, sizeof(buf2), 1, f);
fseek(f, 0, SEEK_SET);
}
clock_gettime(CLOCK_MONOTONIC, &ts2);
d = diff(ts1, ts2);
elapsed = (float)d.tv_sec + ((float)d.tv_nsec * 1e-9);
printf("Frames: %d\n", nloop * 2);
printf("Elapsed: %f\n", elapsed);
printf("Frames per second: %f\n", (float)(nloop * 2) / elapsed);
}
// https://www.guyrutenberg.com/2007/09/22/profiling-code-using-clock_gettime/
struct timespec diff(struct timespec start, struct timespec end) {
struct timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}

View File

@ -50,3 +50,9 @@ injector/AppMain.bin:
@$(AS) injector/disable_mmu.S -o injector/disable_mmu.elf
@./extract.py -p injector/disable_mmu.elf injector/disable_mmu.bin
@./injector/inject.py 0xf00000 0x700000 injector/disable_mmu.bin injector/injected.bin injector/AppMain.bin
injector/uboot.bin:
@$(AS) injector/disable_mmu.S -o injector/disable_mmu.elf
@./extract.py -p injector/disable_mmu.elf injector/disable_mmu.bin
@./extract.py -p injector/disable_mmu.elf injector/disable_mmu.bin
@./injector/inject.py 0xed0000 0x700000 injector/disable_mmu.bin u-boot.bin injector/uboot.bin

View File

@ -15,12 +15,44 @@ _start:
mcr p15, 0, r8, c14, c3, 1
mov r9, #0
mrc p15, 0, r10, c1, c0, 0
@bic r10, r10, #5 @ disable MMU and dcache
bic r10, r10, #1 @ disable MMU
@bic r10, r10, #4096 @ disable icache
mcr p15, 0, r10, c1, c0, 0 // write ctrl regs
#mcr p15, 0, r9, c7, c7, 0 // invalidate cache
#mcr p15, 0, r9, c8, c7, 0 // invalidate TLB
mrc p15, 0, r6, c1, c0, 0
bic r6, r6, #4 @ disable dcache
bic r6, r6, #4096 @ disable icache
mcr p15, 0, r6, c1, c0, 0 // write ctrl regs
mcr p15, 0, r9, c7, c5, 0 // invalidate icache
// from: https://www.aps-web.jp/academy/ca/229/#i-2
mov r10,#0 //
mcr p15,2,r10,c0,c0,0 // CSSELR
//
isb //
mrc p15,1,r1,c0,c0,0 // CCSIDR
and r2,r1,#7 // b001=8ワード/
add r2,r2,#4 // DCISW
ldr r4,=0x3FF //
ands r4,r4,r1,LSR #3 // r4
clz r5,r4 // DCISW
ldr r7,=0x7FFF //
ands r7,r7,r1,LSR #13 // r7
// 0x7F=12Kbyte/0xFF=32Kbyte/0x1FF=64Kbyte
loop2:
mov r9,r4 // r9
loop3:
orr r11,r10,r9,LSL r5 //
orr r11,r11,r7,LSL r2 //
mcr p15,0,r11,c7,c6,2 // DCISW/
//
subs r9,r9,#1 // -1
bge loop3 //
subs r7,r7,#1 // -1
bge loop2 //
mcr p15, 0, r9, c8, c7, 0 // invalidate TLB
mcr p15, 0, r9, c7, c5, 6 // invalidate branch predictor array
bic r6, r6, #1 @ disable MMU
mcr p15, 0, r6, c1, c0, 0 // write ctrl regs
mov pc, r0