From 63e65a252aafd97dd3424167a4a46182d6cbec2e Mon Sep 17 00:00:00 2001 From: Takumi Sueda Date: Sun, 7 Nov 2021 22:01:09 +0900 Subject: [PATCH] Revert "Update x1/c impl" This reverts commit 866afba9c2e862f744df588b50be9eee8d955eb6. --- x1/Makefile | 17 +- x1/c/asm.S | 56 -- x1/c/common.h | 23 - x1/c/console.c | 33 -- x1/c/divmod.S | 22 - x1/c/divmod.c | 151 ----- x1/c/fsl_lpuart.h | 58 -- x1/c/imx-regs.h | 1119 ----------------------------------- x1/c/main.c | 340 +---------- x1/c/main.c.lcd | 24 - x1/c/pcc.h | 371 ------------ x1/c/scg.c | 640 -------------------- x1/c/scg.h | 339 ----------- x1/c/sizes.h | 47 -- x1/injector/disable_mmu.elf | Bin 0 -> 624 bytes x1/injector/injected.elf | Bin 0 -> 584 bytes 16 files changed, 19 insertions(+), 3221 deletions(-) delete mode 100644 x1/c/asm.S delete mode 100644 x1/c/common.h delete mode 100644 x1/c/console.c delete mode 100644 x1/c/divmod.S delete mode 100644 x1/c/divmod.c delete mode 100644 x1/c/fsl_lpuart.h delete mode 100644 x1/c/imx-regs.h delete mode 100644 x1/c/main.c.lcd delete mode 100644 x1/c/pcc.h delete mode 100644 x1/c/scg.c delete mode 100644 x1/c/scg.h delete mode 100644 x1/c/sizes.h create mode 100644 x1/injector/disable_mmu.elf create mode 100644 x1/injector/injected.elf diff --git a/x1/Makefile b/x1/Makefile index ce80d86..be5d381 100644 --- a/x1/Makefile +++ b/x1/Makefile @@ -15,11 +15,10 @@ clean: @./extract.py a.out $@ @rm -f a.out -c/main.elf: - @$(CC) -nostdlib -static -fPIC -marm -O0 c/start.S c/main.c c/scg.c c/divmod.c c/divmod.S -o c/main.elf - -c/main.bin: c/main.elf - @./extract.py c/main.elf $@ +c/main.bin: + @$(CC) -nostdlib -static -fPIC -mcpu=cortex-a7 c/start.S c/main.c + @./extract.py a.out $@ + @rm -f a.out spray/main.bin: @$(AS) spray/top.S @@ -32,12 +31,12 @@ spray/main.bin: @rm -f a.out injector/AppMain.bin: - @if [ "$(ELF)" = "" ]; then \ - echo "Please specify ELF."; \ + @if [ "$(INJECTED_S)" = "" ]; then \ + echo "Please specify INJECTED_S."; \ exit 1; \ fi - @$(STRIP) $(ELF) - @./extract.py $(ELF) injector/injected.bin + @$(AS) $(INJECTED_S) -o injector/injected.elf + @./extract.py -p injector/injected.elf injector/injected.bin @$(AS) injector/disable_mmu.S -o injector/disable_mmu.elf @./extract.py -p injector/disable_mmu.elf injector/disable_mmu.bin @./injector/inject.py 0xf00000 0x700000 injector/disable_mmu.bin injector/injected.bin injector/AppMain.bin diff --git a/x1/c/asm.S b/x1/c/asm.S deleted file mode 100644 index 584f70a..0000000 --- a/x1/c/asm.S +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ -/* - * Copyright (c) 2014, STMicroelectronics International N.V. - * Copyright (c) 2020, Linaro Limited - */ - -#if defined(CFG_UNWIND) && defined(__arm__) -#define UNWIND(...) __VA_ARGS__ -#else -#define UNWIND(...) -#endif - - .macro FUNC name colon section=default align=4 - .ifc \section\(),default - .section .text.\name - .else - .section \section , "ax" , %progbits - .endif - .global \name - .type \name , %function - .balign \align - \name \colon -UNWIND( .fnstart) - .endm - - .macro DATA name colon - .global \name - .type \name , %object - \name \colon - .endm - - .macro LOCAL_FUNC name colon section=default align=4 - .ifc \section\(),default - .section .text.\name - .else - .section \section , "ax" , %progbits - .endif - .type \name , %function - .balign \align - \name \colon -UNWIND( .fnstart) - .endm - - .macro LOCAL_DATA name colon - .type \name , %object - \name \colon - .endm - - .macro END_DATA name - .size \name , .-\name - .endm - - .macro END_FUNC name -UNWIND( .fnend) - .size \name , .-\name - .endm diff --git a/x1/c/common.h b/x1/c/common.h deleted file mode 100644 index 5c136c2..0000000 --- a/x1/c/common.h +++ /dev/null @@ -1,23 +0,0 @@ -#pragma pack(1) - -#define readl(a) (*(volatile unsigned int *)(a)) -#define writel(v, a) (*(volatile unsigned int *)(a) = (v)) - -typedef unsigned int u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef struct _pixel_t { - u8 r; - u8 g; - u8 b; -} pixel_t; - -#define pack_pixel(p) (((u16)(p.r & 0x1f) << 11) | ((u16)(p.g & 0x3f) << 5) | ((u16)(p.b & 0x1f))) - -#define WNATIVE 10 -#define HNATIVE 854 - -void rot(u16* x, u16* y); -void prepare_fb(u16** fb); -void bitblt(u16** fb, pixel_t px, u16 x, u16 y); diff --git a/x1/c/console.c b/x1/c/console.c deleted file mode 100644 index 2365e15..0000000 --- a/x1/c/console.c +++ /dev/null @@ -1,33 +0,0 @@ -#include "common.h" - -void rot(u16* x, u16* y) { - u16 nx, ny; - nx = WNATIVE - ny; - ny = nx; - *x = nx; - *y = ny; -} - -void prepare_fb(u16** fb) { - int x, y; - u16 px = 0b1111100000000000; - - fb[0][0] = 0x2a; - fb[0][1] = 0x00; - fb[0][2] = 0x00; - fb[0][3] = 0x2b; - fb[0][4] = 0x00; - fb[0][5] = 0x00; - fb[0][6] = 0x2c; - - for (y=0; yr = 0xFFFFFFFF; /* division by 0 */ - return; - } - - while ((p >> 31) == 0) { - i = i << 1; /* count the max division steps */ - p = p << 1; /* increase p until it has maximum size*/ - } - - while (i > 0) { - q = q << 1; /* write bit in q at index (size-1) */ - if (n >= p) - { - n -= p; - q++; - } - p = p >> 1; /* decrease p */ - i = i >> 1; /* decrease remaining size in q */ - } - qr->r = n; - qr->q = q; -} - -static void uint_div_qr(unsigned numerator, unsigned denominator, struct qr *qr) -{ - - division_qr(numerator, denominator, qr); - - /* negate quotient and/or remainder according to requester */ - if (qr->q_n) - qr->q = -qr->q; - if (qr->r_n) - qr->r = -qr->r; -} - -unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator) -{ - struct qr qr = { .q_n = 0, .r_n = 0 }; - - uint_div_qr(numerator, denominator, &qr); - - return qr.q; -} - -unsigned __aeabi_uidivmod(unsigned numerator, unsigned denominator) -{ - struct qr qr = { .q_n = 0, .r_n = 0 }; - - uint_div_qr(numerator, denominator, &qr); - - return ret_uidivmod_values(qr.q, qr.r); -} - -signed __aeabi_idiv(signed numerator, signed denominator) -{ - struct qr qr = { .q_n = 0, .r_n = 0 }; - - if (((numerator < 0) && (denominator > 0)) || - ((numerator > 0) && (denominator < 0))) - qr.q_n = 1; /* quotient shall be negate */ - if (numerator < 0) { - numerator = -numerator; - qr.r_n = 1; /* remainder shall be negate */ - } - if (denominator < 0) - denominator = -denominator; - - uint_div_qr(numerator, denominator, &qr); - - return qr.q; -} - -signed __aeabi_idivmod(signed numerator, signed denominator) -{ - struct qr qr = { .q_n = 0, .r_n = 0 }; - - if (((numerator < 0) && (denominator > 0)) || - ((numerator > 0) && (denominator < 0))) - qr.q_n = 1; /* quotient shall be negate */ - if (numerator < 0) { - numerator = -numerator; - qr.r_n = 1; /* remainder shall be negate */ - } - if (denominator < 0) - denominator = -denominator; - - uint_div_qr(numerator, denominator, &qr); - - return ret_idivmod_values(qr.q, qr.r); -} diff --git a/x1/c/fsl_lpuart.h b/x1/c/fsl_lpuart.h deleted file mode 100644 index 7f5ada5..0000000 --- a/x1/c/fsl_lpuart.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ - -struct lpuart_fsl_reg32 { - u32 verid; - u32 param; - u32 global; - u32 pincfg; - u32 baud; - u32 stat; - u32 ctrl; - u32 data; - u32 match; - u32 modir; - u32 fifo; - u32 water; -}; - -struct lpuart_fsl { - u8 ubdh; - u8 ubdl; - u8 uc1; - u8 uc2; - u8 us1; - u8 us2; - u8 uc3; - u8 ud; - u8 uma1; - u8 uma2; - u8 uc4; - u8 uc5; - u8 ued; - u8 umodem; - u8 uir; - u8 reserved; - u8 upfifo; - u8 ucfifo; - u8 usfifo; - u8 utwfifo; - u8 utcfifo; - u8 urwfifo; - u8 urcfifo; - u8 rsvd[28]; -}; - -/* Used on i.MX7ULP */ -#define LPUART_BAUD_BOTHEDGE_MASK (0x20000) -#define LPUART_BAUD_OSR_MASK (0x1F000000) -#define LPUART_BAUD_OSR_SHIFT (24) -#define LPUART_BAUD_OSR(x) ((((u32)(x)) << 24) & 0x1F000000) -#define LPUART_BAUD_SBR_MASK (0x1FFF) -#define LPUART_BAUD_SBR_SHIFT (0U) -#define LPUART_BAUD_SBR(x) (((u32)(x)) & 0x1FFF) -#define LPUART_BAUD_M10_MASK (0x20000000U) -#define LPUART_BAUD_SBNS_MASK (0x2000U) diff --git a/x1/c/imx-regs.h b/x1/c/imx-regs.h deleted file mode 100644 index 8e5eb6a..0000000 --- a/x1/c/imx-regs.h +++ /dev/null @@ -1,1119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _MX7ULP_REGS_H_ -#define _MX7ULP_REGS_H_ - -#include "sizes.h" - -#define CAAM_SEC_SRAM_BASE (0x26000000) -#define CAAM_SEC_SRAM_SIZE (SZ_32K) -#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) - -#define OCRAM_0_BASE (0x2F000000) -#define OCRAM_0_SIZE (SZ_128K) -#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) - -#define OCRAM_1_BASE (0x2F020000) -#define OCRAM_1_SIZE (SZ_128K) -#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) - -#define TCML_BASE (0x1FFD0000) -#define TCMU_BASE (0x20000000) - -#define AIPS3_BASE (0x40800000UL) -#define AIPS3_SLOT_SIZE (SZ_64K) -#define AIPS2_BASE (0x40000000UL) -#define AIPS2_SLOT_SIZE (SZ_64K) -#define AIPS1_BASE (0x41080000UL) -#define AIPS1_SLOT_SIZE (SZ_4K) -#define AIPS0_BASE (0x41000000UL) -#define AIPS0_SLOT_SIZE (SZ_4K) -#define IOMUXC0_AIPS0_SLOT (61) -#define WDG0_AIPS0_SLOT (37) -#define WDG1_AIPS2_SLOT (61) -#define WDG2_AIPS2_SLOT (67) -#define WDG0_PCC0_SLOT (37) -#define IOMUXC1_AIPS3_SLOT (44) -#define CMC0_AIPS1_SLOT (36) -#define CMC1_AIPS2_SLOT (65) -#define SCG0_AIPS0_SLOT (39) -#define PCC0_AIPS0_SLOT (38) -#define PCC1_AIPS1_SLOT (50) -#define PCC2_AIPS2_SLOT (63) -#define PCC3_AIPS3_SLOT (51) -#define SCG1_AIPS2_SLOT (62) -#define SIM0_AIPS1_SLOT (35) -#define SIM1_AIPS1_SLOT (48) -#define USBOTG0_AIPS2_SLOT (51) -#define USBOTG1_AIPS2_SLOT (52) -#define USBPHY_AIPS2_SLOT (53) -#define USDHC0_AIPS2_SLOT (55) -#define USDHC1_AIPS2_SLOT (56) -#define RGPIO2P0_AIPS0_SLOT (15) -#define RGPIO2P1_AIPS2_SLOT (15) -#define IOMUXC0_AIPS0_SLOT (61) -#define OCOTP_CTRL_AIPS1_SLOT (38) -#define OCOTP_CTRL_PCC1_SLOT (38) -#define SIM1_PCC1_SLOT (48) -#define MMDC0_AIPS3_SLOT (43) -#define IOMUXC_DDR_AIPS3_SLOT (45) - -#define LPI2C0_AIPS0_SLOT (51) -#define LPI2C1_AIPS0_SLOT (52) -#define LPI2C2_AIPS0_SLOT (53) -#define LPI2C3_AIPS0_SLOT (54) -#define LPI2C4_AIPS2_SLOT (43) -#define LPI2C5_AIPS2_SLOT (44) -#define LPI2C6_AIPS3_SLOT (36) -#define LPI2C7_AIPS3_SLOT (37) - -#define LPUART0_PCC0_SLOT (58) -#define LPUART1_PCC0_SLOT (59) -#define LPUART2_PCC1_SLOT (43) -#define LPUART3_PCC1_SLOT (44) -#define LPUART0_AIPS0_SLOT (58) -#define LPUART1_AIPS0_SLOT (59) -#define LPUART2_AIPS1_SLOT (43) -#define LPUART3_AIPS1_SLOT (44) -#define LPUART4_AIPS2_SLOT (45) -#define LPUART5_AIPS2_SLOT (46) -#define LPUART6_AIPS3_SLOT (38) -#define LPUART7_AIPS3_SLOT (39) - -#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) -#define CORE_B_ROM_BASE (0x00000000) - -#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE -#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE -#define IRAM_BASE_ADDR OCRAM_0_BASE -#define IRAM_SIZE (SZ_128K + SZ_128K) - -#define IOMUXC_PCR_MUX_ALT0 (0<<8) -#define IOMUXC_PCR_MUX_ALT1 (1<<8) -#define IOMUXC_PCR_MUX_ALT2 (2<<8) -#define IOMUXC_PCR_MUX_ALT3 (3<<8) -#define IOMUXC_PCR_MUX_ALT4 (4<<8) -#define IOMUXC_PCR_MUX_ALT5 (5<<8) -#define IOMUXC_PCR_MUX_ALT6 (6<<8) -#define IOMUXC_PCR_MUX_ALT7 (7<<8) -#define IOMUXC_PCR_MUX_ALT8 (8<<8) -#define IOMUXC_PCR_MUX_ALT9 (9<<8) -#define IOMUXC_PCR_MUX_ALT10 (10<<8) -#define IOMUXC_PCR_MUX_ALT11 (11<<8) -#define IOMUXC_PCR_MUX_ALT12 (12<<8) -#define IOMUXC_PCR_MUX_ALT13 (13<<8) -#define IOMUXC_PCR_MUX_ALT14 (14<<8) -#define IOMUXC_PCR_MUX_ALT15 (15<<8) - -#define IOMUXC_PSMI_IMUX_ALT0 (0x0) -#define IOMUXC_PSMI_IMUX_ALT1 (0x1) -#define IOMUXC_PSMI_IMUX_ALT2 (0x2) -#define IOMUXC_PSMI_IMUX_ALT3 (0x3) -#define IOMUXC_PSMI_IMUX_ALT4 (0x4) -#define IOMUXC_PSMI_IMUX_ALT5 (0x5) -#define IOMUXC_PSMI_IMUX_ALT6 (0x6) -#define IOMUXC_PSMI_IMUX_ALT7 (0x7) - - -#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) -#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) -#define SIM_SOPT1_A7_SW_RESET (1<<0) - -#define IOMUXC_PCR_MUX_ALT_SHIFT (8) -#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) -#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) - -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) -#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) -#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) -#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) -#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) -#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) -#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) -#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) -#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) -#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ -#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) -#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) -#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) -#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) -#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) -#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) - -#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) -#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) -#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) -#define USB_PHY0_BASE_ADDR USBPHY_RBASE -#define USB_BASE_ADDR USBOTG0_RBASE - -#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) -#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) -#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) -#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) -#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) -#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) -#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) -#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) - -#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) -#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) -#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) -#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) -#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) -#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) -#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) -#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) - -#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) -#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) - -#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) -#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) - -#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) -#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) -#define CMC0_SRS (CMC0_RBASE + 0x20) -#define CMC0_SSRS (CMC0_RBASE + 0x28) -#define CMC1_SRS (CMC1_RBASE + 0x20) -#define CMC1_SSRS (CMC1_RBASE + 0x28) - -#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) -#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) -#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) -#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) -#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) -#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) -#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) - -#define SCG_CSR (SCG0_RBASE + 0x010) -#define SCG_RCCR (SCG0_RBASE + 0x014) -#define SCG_VCCR (SCG0_RBASE + 0x018) -#define SCG_HCCR (SCG0_RBASE + 0x01c) - -#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) -#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) -#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) -#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) -#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) -#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) -#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) -#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) - -#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) -#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) - -#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) -#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) - -#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) - -#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) -#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) - -#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) -#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) -#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) -#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) - - -#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) -#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) -#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) -#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) -#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) -#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) -#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) -#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) -#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) -#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) -#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) -#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) -#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) -#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) -#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) -#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) -#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) -#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) -#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) -#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) -#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) -#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) -#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) -#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) -#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) -#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) -#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) -#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) -#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) -#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) -#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) -#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) - -/* Remap the rgpio2p registers addr to driver's addr */ -#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE -#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) -#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) -#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) -#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) -#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) - -/* MMDC registers addresses */ -#define MMDC_MDCTL_OFFSET (0x000) -#define MMDC_MDPDC_OFFSET (0x004) -#define MMDC_MDOTC_OFFSET (0x008) -#define MMDC_MDCFG0_OFFSET (0x00C) -#define MMDC_MDCFG1_OFFSET (0x010) -#define MMDC_MDCFG2_OFFSET (0x014) -#define MMDC_MDMISC_OFFSET (0x018) -#define MMDC_MDSCR_OFFSET (0x01C) -#define MMDC_MDREF_OFFSET (0x020) -#define MMDC_MDRWD_OFFSET (0x02C) -#define MMDC_MDOR_OFFSET (0x030) -#define MMDC_MDMRR_OFFSET (0x034) -#define MMDC_MDCFG3LP_OFFSET (0x038) -#define MMDC_MDMR4_OFFSET (0x03C) -#define MMDC_MDASP_OFFSET (0x040) - -#define MMDC_MAARCR_OFFSET (0x400) -#define MMDC_MAPSR_OFFSET (0x404) -#define MMDC_MAEXIDR0_OFFSET (0x408) -#define MMDC_MAEXIDR1_OFFSET (0x40C) -#define MMDC_MADPCR0_OFFSET (0x410) -#define MMDC_MADPCR1_OFFSET (0x414) -#define MMDC_MADPSR0_OFFSET (0x418) -#define MMDC_MADPSR1_OFFSET (0x41C) -#define MMDC_MADPSR2_OFFSET (0x420) -#define MMDC_MADPSR3_OFFSET (0x424) -#define MMDC_MADPSR4_OFFSET (0x428) -#define MMDC_MADPSR5_OFFSET (0x42C) -#define MMDC_MASBS0_OFFSET (0x430) -#define MMDC_MASBS1_OFFSET (0x434) -#define MMDC_MAGENP_OFFSET (0x440) - -#define MMDC_MPZQHWCTRL_OFFSET (0x800) -#define MMDC_MPZQSWCTRL_OFFSET (0x804) -#define MMDC_MPWLGCR_OFFSET (0x808) -#define MMDC_MPWLDECTRL0_OFFSET (0x80C) -#define MMDC_MPWLDECTRL1_OFFSET (0x810) -#define MMDC_MPWLDLST_OFFSET (0x814) -#define MMDC_MPODTCTRL_OFFSET (0x818) -#define MMDC_MPREDQBY0DL_OFFSET (0x81C) -#define MMDC_MPREDQBY1DL_OFFSET (0x820) -#define MMDC_MPREDQBY2DL_OFFSET (0x824) -#define MMDC_MPREDQBY3DL_OFFSET (0x828) -#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) -#define MMDC_MPWRDQBY1DL_OFFSET (0x830) -#define MMDC_MPWRDQBY2DL_OFFSET (0x834) -#define MMDC_MPWRDQBY3DL_OFFSET (0x838) -#define MMDC_MPDGCTRL0_OFFSET (0x83C) -#define MMDC_MPDGCTRL1_OFFSET (0x840) -#define MMDC_MPDGDLST_OFFSET (0x844) -#define MMDC_MPRDDLCTL_OFFSET (0x848) -#define MMDC_MPRDDLST_OFFSET (0x84C) -#define MMDC_MPWRDLCTL_OFFSET (0x850) -#define MMDC_MPWRDLST_OFFSET (0x854) -#define MMDC_MPSDCTRL_OFFSET (0x858) -#define MMDC_MPZQLP2CTL_OFFSET (0x85C) -#define MMDC_MPRDDLHWCTL_OFFSET (0x860) -#define MMDC_MPWRDLHWCTL_OFFSET (0x864) -#define MMDC_MPRDDLHWST0_OFFSET (0x868) -#define MMDC_MPRDDLHWST1_OFFSET (0x86C) -#define MMDC_MPWRDLHWST0_OFFSET (0x870) -#define MMDC_MPWRDLHWST1_OFFSET (0x874) -#define MMDC_MPWLHWERR_OFFSET (0x878) -#define MMDC_MPDGHWST0_OFFSET (0x87C) -#define MMDC_MPDGHWST1_OFFSET (0x880) -#define MMDC_MPDGHWST2_OFFSET (0x884) -#define MMDC_MPDGHWST3_OFFSET (0x888) -#define MMDC_MPPDCMPR1_OFFSET (0x88C) -#define MMDC_MPPDCMPR2_OFFSET (0x890) -#define MMDC_MPSWDAR_OFFSET (0x894) -#define MMDC_MPSWDRDR0_OFFSET (0x898) -#define MMDC_MPSWDRDR1_OFFSET (0x89C) -#define MMDC_MPSWDRDR2_OFFSET (0x8A0) -#define MMDC_MPSWDRDR3_OFFSET (0x8A4) -#define MMDC_MPSWDRDR4_OFFSET (0x8A8) -#define MMDC_MPSWDRDR5_OFFSET (0x8AC) -#define MMDC_MPSWDRDR6_OFFSET (0x8B0) -#define MMDC_MPSWDRDR7_OFFSET (0x8B4) -#define MMDC_MPMUR_OFFSET (0x8B8) -#define MMDC_MPWRCADL_OFFSET (0x8BC) -#define MMDC_MPDCCR_OFFSET (0x8C0) -#define MMDC_MPBC_OFFSET (0x8C4) -#define MMDC_MPSWDRAR_OFFSET (0x8C8) - -/* First MMDC invalid IPS address */ -#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) -#define MMDC_REGS_BASE MMDC0_RBASE - -#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) -#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) -#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) -#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) -#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) -#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) -#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) -#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) -#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) -#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) -#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) -#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) -#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) -#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) -#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) - -#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) -#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) -#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) -#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) -#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) -#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) -#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) -#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) -#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) -#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) -#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) -#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) -#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) -#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) -#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) - -#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) -#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) -#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) -#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) -#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) -#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) -#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) -#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) -#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) -#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) -#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) -#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) -#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) -#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) -#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) -#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) -#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) -#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) -#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) -#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) -#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) -#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) -#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) -#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) -#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) -#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) -#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) -#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) -#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) -#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) -#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) -#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) -#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) -#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) -#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) -#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) -#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) -#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) -#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) -#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) -#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) -#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) -#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) -#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) -#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) -#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) -#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) -#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) -#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) -#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) -#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) - -/* MMDC registers bit defines */ -#define MMDC_MDCTL_SDE_0 (31) -#define MMDC_MDCTL_SDE_1 (30) -#define MMDC_MDCTL_ROW (24) -#define MMDC_MDCTL_COL (20) -#define MMDC_MDCTL_BL (19) -#define MMDC_MDCTL_DSIZ (16) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY (31) -#define MMDC_MDMISC_CS1_RDY (30) -#define MMDC_MDMISC_CK1_DEL (22) -#define MMDC_MDMISC_CK1_GATING (21) -#define MMDC_MDMISC_CALIB_PER_CS (20) -#define MMDC_MDMISC_ADDR_MIRROR (19) -#define MMDC_MDMISC_LHD (18) -#define MMDC_MDMISC_WALAT (16) -#define MMDC_MDMISC_BI (12) -#define MMDC_MDMISC_LPDDR2_S (11) -#define MMDC_MDMISC_MIF3_MODE (9) -#define MMDC_MDMISC_RALAT (6) -#define MMDC_MDMISC_DDR_4_BANK (5) -#define MMDC_MDMISC_DDR_TYPE (3) -#define MMDC_MDMISC_RST (1) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR (8) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB (24) -#define MMDC_MDSCR_MR_OP (24) -#define MMDC_MDSCR_CMD_ADDR_LSB (16) -#define MMDC_MDSCR_MR_ADDR (16) -#define MMDC_MDSCR_CON_REQ (15) -#define MMDC_MDSCR_CON_ACK (14) -#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) -#define MMDC_MDSCR_WL_EN (9) -#define MMDC_MDSCR_CMD (4) -#define MMDC_MDSCR_CMD_CS (3) -#define MMDC_MDSCR_CMD_BA (0) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) -#define MMDC_MPZQHWCTRL_ZQ_MODE (0) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) -#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) -#define MMDC_MPDGCTRL0_DG_DIS (29) -#define MMDC_MPDGCTRL0_HW_DG_EN (28) -#define MMDC_MPDGCTRL0_HW_DG_ERR (12) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) -#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) -#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) -#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) -#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) -#define MMDC_MPSWDAR_SW_DUMMY_RD (1) -#define MMDC_MPSWDAR_SW_DUMMY_WR (0) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS (9) -#define MMDC_MADPCR0_SBS_EN (8) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD (0) -#define MMDC_MASBS1_SBS_TYPE (1) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT (16) -#define MMDC_MDREF_REF_SEL (14) -#define MMDC_MDREF_REFR (11) -#define MMDC_MDREF_START_REF (0) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN (0) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN (0) -#define MMDC_MPBC_BIST_CA0_LP_EN (1) -#define MMDC_MPBC_BIST_DQ0_LP_EN (3) -#define MMDC_MPBC_BIST_DQ1_LP_EN (4) -#define MMDC_MPBC_BIST_DQ2_LP_EN (5) -#define MMDC_MPBC_BIST_DQ3_LP_EN (6) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR (11) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK (25) -#define MMDC_MAPSR_LPACK (24) -#define MMDC_MAPSR_DVFS (21) -#define MMDC_MAPSR_LPMD (20) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP (16) -#define MMDC_MDCFG3LP_tRCD_LP (8) -#define MMDC_MDCFG3LP_tRPpb_LP (4) -#define MMDC_MDCFG3LP_tRPab_LP (0) - -/* MDOR */ -#define MMDC_MDOR_tXPR (16) -#define MMDC_MDOR_SDE_to_RST (8) -#define MMDC_MDOR_RST_to_CKE (0) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC (24) -#define MMDC_MDCFG0_tXS (16) -#define MMDC_MDCFG0_tXP (13) -#define MMDC_MDCFG0_tXPDLL (9) -#define MMDC_MDCFG0_tFAW (4) -#define MMDC_MDCFG0_tCL (0) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD (29) -#define MMDC_MDCFG1_tRP (26) -#define MMDC_MDCFG1_tRC (21) -#define MMDC_MDCFG1_tRAS (16) -#define MMDC_MDCFG1_tRPA (15) -#define MMDC_MDCFG1_tWR (9) -#define MMDC_MDCFG1_tMRD (5) -#define MMDC_MDCFG1_tCWL (0) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK (16) -#define MMDC_MDCFG2_tRTP (6) -#define MMDC_MDCFG2_tWTR (3) -#define MMDC_MDCFG2_tRRD (0) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI (16) -#define MMDC_MDRWD_RTW_SAME (12) -#define MMDC_MDRWD_WTR_DIFF (9) -#define MMDC_MDRWD_WTW_DIFF (6) -#define MMDC_MDRWD_RTW_DIFF (3) -#define MMDC_MDRWD_RTR_DIFF (0) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1 (28) -#define MMDC_MDPDC_PRCT_0 (24) -#define MMDC_MDPDC_tCKE (16) -#define MMDC_MDPDC_PWDT_1 (12) -#define MMDC_MDPDC_PWDT_0 (8) -#define MMDC_MDPDC_SLOW_PD (7) -#define MMDC_MDPDC_BOTH_CS_PD (6) -#define MMDC_MDPDC_tCKSRX (3) -#define MMDC_MDPDC_tCKSRE (0) - -/* MDASP */ -#define MMDC_MDASP_CS0_END (0) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) - -/* Fields masks */ -#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) -#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) -#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) -#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) -#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) -#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) -#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) -#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) -#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) -#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) -#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) -#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) -#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) -#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) -#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) -#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) -#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) -#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) -#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) -#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) -#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) -#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) -#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) -#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) -#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) -#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) -#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) -#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) -#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) -#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) -#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) -#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) -#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) -#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) -#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) -#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) -#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) -#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) -#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) -#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) -#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) -#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) -#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) -#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) -#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) -#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) -#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) -#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) -#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) -#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) -#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) -#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) -#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) -#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) -#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) -#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) -#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) -#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) - -/* MDOR */ -#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) -#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) -#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) -#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) -#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) -#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) -#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) -#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) -#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) -#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) -#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) -#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) -#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) -#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) -#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) -#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) -#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) -#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) -#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) -#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) -#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) -#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) -#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) -#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) -#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) -#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) -#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) -#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) -#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) -#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) -#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) - -/* MDASP */ -#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - -#include - -struct fuse_word { - u32 fuse; - u32 rsvd[3]; -}; - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 pdn; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 out_status; - u32 out_status_set; - u32 out_status_clr; - u32 out_status_tog; - u32 startword; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[19]; - struct fuse_word mem_repair[8]; - u32 rsvd7[0xa8]; - - /* fuse banks */ - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[0]; -}; - -struct fuse_bank1_regs { - u32 lock0; - u32 rsvd0[3]; - u32 lock1; - u32 rsvd1[3]; - u32 lock2; - u32 rsvd2[3]; - u32 cfg0; - u32 rsvd3[3]; - u32 cfg1; - u32 rsvd4[3]; - u32 cfg2; - u32 rsvd5[3]; - u32 cfg3; - u32 rsvd6[3]; - u32 cfg4; - u32 rsvd7[3]; -}; - -struct fuse_bank2_regs { - struct fuse_word boot[8]; -}; - -struct fuse_bank3_regs { - u32 mem0; - u32 rsvd0[3]; - u32 mem1; - u32 rsvd1[3]; - u32 mem2; - u32 rsvd2[3]; - u32 mem3; - u32 rsvd3[3]; - u32 ana0; - u32 rsvd4[3]; - u32 ana1; - u32 rsvd5[3]; - u32 ana2; - u32 rsvd6[3]; - u32 ana3; - u32 rsvd7[3]; -}; - -struct fuse_bank7_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 gp0; - u32 rsvd2[3]; - u32 gp1; - u32 rsvd3[3]; - u32 gp2; - u32 rsvd4[3]; - u32 gp3; - u32 rsvd5[3]; - u32 gp4; - u32 rsvd6[3]; - u32 gp5; - u32 rsvd7[3]; -}; - -struct usbphy_regs { - u32 usbphy_pwd; /* 0x000 */ - u32 usbphy_pwd_set; /* 0x004 */ - u32 usbphy_pwd_clr; /* 0x008 */ - u32 usbphy_pwd_tog; /* 0x00c */ - u32 usbphy_tx; /* 0x010 */ - u32 usbphy_tx_set; /* 0x014 */ - u32 usbphy_tx_clr; /* 0x018 */ - u32 usbphy_tx_tog; /* 0x01c */ - u32 usbphy_rx; /* 0x020 */ - u32 usbphy_rx_set; /* 0x024 */ - u32 usbphy_rx_clr; /* 0x028 */ - u32 usbphy_rx_tog; /* 0x02c */ - u32 usbphy_ctrl; /* 0x030 */ - u32 usbphy_ctrl_set; /* 0x034 */ - u32 usbphy_ctrl_clr; /* 0x038 */ - u32 usbphy_ctrl_tog; /* 0x03c */ - u32 usbphy_status; /* 0x040 */ - u32 reserved0[3]; - u32 usbphy_debug0; /* 0x050 */ - u32 usbphy_debug0_set; /* 0x054 */ - u32 usbphy_debug0_clr; /* 0x058 */ - u32 usbphy_debug0_tog; /* 0x05c */ - u32 reserved1[4]; - u32 usbphy_debug1; /* 0x070 */ - u32 usbphy_debug1_set; /* 0x074 */ - u32 usbphy_debug1_clr; /* 0x078 */ - u32 usbphy_debug1_tog; /* 0x07c */ - u32 usbphy_version; /* 0x080 */ - u32 reserved2[7]; - u32 usb1_pll_480_ctrl; /* 0x0a0 */ - u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ - u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ - u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ - u32 reserved3[4]; - u32 usb1_vbus_detect; /* 0xc0 */ - u32 usb1_vbus_detect_set; /* 0xc4 */ - u32 usb1_vbus_detect_clr; /* 0xc8 */ - u32 usb1_vbus_detect_tog; /* 0xcc */ - u32 usb1_vbus_det_stat; /* 0xd0 */ - u32 reserved4[3]; - u32 usb1_chrg_detect; /* 0xe0 */ - u32 usb1_chrg_detect_set; /* 0xe4 */ - u32 usb1_chrg_detect_clr; /* 0xe8 */ - u32 usb1_chrg_detect_tog; /* 0xec */ - u32 usb1_chrg_det_stat; /* 0xf0 */ - u32 reserved5[3]; - u32 usbphy_anactrl; /* 0x100 */ - u32 usbphy_anactrl_set; /* 0x104 */ - u32 usbphy_anactrl_clr; /* 0x108 */ - u32 usbphy_anactrl_tog; /* 0x10c */ - u32 usb1_loopback; /* 0x110 */ - u32 usb1_loopback_set; /* 0x114 */ - u32 usb1_loopback_clr; /* 0x118 */ - u32 usb1_loopback_tog; /* 0x11c */ - u32 usb1_loopback_hsfscnt; /* 0x120 */ - u32 usb1_loopback_hsfscnt_set; /* 0x124 */ - u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ - u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ - u32 usphy_trim_override_en; /* 0x130 */ - u32 usphy_trim_override_en_set; /* 0x134 */ - u32 usphy_trim_override_en_clr; /* 0x138 */ - u32 usphy_trim_override_en_tog; /* 0x13c */ - u32 usb1_pfda_ctrl1; /* 0x140 */ - u32 usb1_pfda_ctrl1_set; /* 0x144 */ - u32 usb1_pfda_ctrl1_clr; /* 0x148 */ - u32 usb1_pfda_ctrl1_tog; /* 0x14c */ -}; - - -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) -#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) - -#endif - -#endif /* _MX7ULP_REGS_H_*/ diff --git a/x1/c/main.c b/x1/c/main.c index ba9bfc8..04205a4 100644 --- a/x1/c/main.c +++ b/x1/c/main.c @@ -1,332 +1,14 @@ -#include "common.h" -#include "pcc.h" -#include "imx-regs.h" -#include "fsl_lpuart.h" - -#define US1_TDRE (1 << 7) -#define US1_RDRF (1 << 5) -#define US1_OR (1 << 3) -#define UC2_TE (1 << 3) -#define UC2_RE (1 << 2) -#define CFIFO_TXFLUSH (1 << 7) -#define CFIFO_RXFLUSH (1 << 6) -#define SFIFO_RXOF (1 << 2) -#define SFIFO_RXUF (1 << 0) - -#define STAT_LBKDIF (1 << 31) -#define STAT_RXEDGIF (1 << 30) -#define STAT_TDRE (1 << 23) -#define STAT_RDRF (1 << 21) -#define STAT_IDLE (1 << 20) -#define STAT_OR (1 << 19) -#define STAT_NF (1 << 18) -#define STAT_FE (1 << 17) -#define STAT_PF (1 << 16) -#define STAT_MA1F (1 << 15) -#define STAT_MA2F (1 << 14) -#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \ - STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F) - -#define CTRL_ORIE (1 << 27) -#define CTRL_NEIE (1 << 26) -#define CTRL_FEIE (1 << 25) -#define CTRL_PEIE (1 << 24) -#define CTRL_TIE (1 << 23) -#define CTRL_TCIE (1 << 22) -#define CTRL_RIE (1 << 21) -#define CTRL_ILIE (1 << 20) -#define CTRL_TE (1 << 19) -#define CTRL_RE (1 << 18) -#define CTRL_MA1IE (1 << 15) -#define CTRL_MA2IE (1 << 14) - -#define FIFO_TXOFE (1 << 9) -#define FIFO_RXUFE (1 << 8) -#define FIFO_TXFE (1 << 7) -#define FIFO_RXFE (1 << 3) - -static struct lpuart_fsl_reg32* regs[] = { - (struct lpuart_fsl_reg32*)0x4103A000, - (struct lpuart_fsl_reg32*)0x4103B000, - (struct lpuart_fsl_reg32*)0x410AB000, - (struct lpuart_fsl_reg32*)0x410AC000, - (struct lpuart_fsl_reg32*)0x402D0000, - (struct lpuart_fsl_reg32*)0x402E0000, - (struct lpuart_fsl_reg32*)0x40A60000, - (struct lpuart_fsl_reg32*)0x40A70000, -}; - -static void lpuart_read32(u32 *addr, u32 *val) { - *(u32 *)val = readl(addr); -} - -static void lpuart_write32(u32 *addr, u32 val) { - writel(val, addr); -} - -// clk - -static enum scg_clk pcc_clksrc[2][7] = { - { - SCG_NIC1_BUS_CLK, - SCG_NIC1_CLK, - SCG_DDR_CLK, - SCG_APLL_PFD2_CLK, - SCG_APLL_PFD1_CLK, - SCG_APLL_PFD0_CLK, - USB_PLL_OUT, - }, - { - SCG_SOSC_DIV2_CLK, - MIPI_PLL_OUT, - SCG_FIRC_DIV2_CLK, - SCG_ROSC_CLK, - SCG_NIC1_BUS_CLK, - SCG_NIC1_CLK, - SCG_APLL_PFD3_CLK, - }, -}; - -static struct pcc_entry pcc_arrays[] = { - {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, - {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, - {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, - {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, - {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, - {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, - - {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, - {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, - {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, - {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, - {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, - {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, -}; - -int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src) -{ - u32 reg, val, clksrc_type; - - clksrc_type = pcc_arrays[clk].clksrc; - if (clksrc_type >= CLKSRC_NO_PCS) { - return 1; - } - - reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; - val = readl(reg); - - if (!(val & PCC_PR_MASK)) { - return 2; - } - - val &= PCC_PCS_MASK; - val = (val >> PCC_PCS_OFFSET); - - if (!val) { - return 3; - } - - *src = pcc_clksrc[clksrc_type][val - 1]; - return 0; -} - -u32 pcc_clock_get_rate(enum pcc_clk clk) -{ - u32 reg, val, rate, frac, div; - enum scg_clk parent; - int ret; - - ret = pcc_clock_get_clksrc(clk, &parent); - if (ret) - return 0; - - rate = scg_clk_get_rate(parent); - - if (pcc_arrays[clk].div == PCC_HAS_DIV) { - reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; - val = readl(reg); - - frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; - div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET; - - rate = rate * (frac + 1) / (div + 1); - } - - return rate; -} - -static void setbrg(struct lpuart_fsl_reg32* reg, int baudrate) -{ - u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; - u32 clk = pcc_clock_get_rate(PER_CLK_LPUART4); - - baud_diff = baudrate; - osr = 0; - sbr = 0; - - for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { - tmp_sbr = (clk / (baudrate * tmp_osr)); - - if (tmp_sbr == 0) - tmp_sbr = 1; - - /*calculate difference in actual buad w/ current values */ - tmp_diff = (clk / (tmp_osr * tmp_sbr)); - tmp_diff = tmp_diff - baudrate; - - /* select best values between sbr and sbr+1 */ - if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) { - tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1))); - tmp_sbr++; - } - - if (tmp_diff <= baud_diff) { - baud_diff = tmp_diff; - osr = tmp_osr; - sbr = tmp_sbr; - } - } - - tmp = readl(®->baud); - - if ((osr > 3) && (osr < 8)) - tmp |= LPUART_BAUD_BOTHEDGE_MASK; - - tmp &= ~LPUART_BAUD_OSR_MASK; - tmp |= LPUART_BAUD_OSR(osr-1); - - tmp &= ~LPUART_BAUD_SBR_MASK; - tmp |= LPUART_BAUD_SBR(sbr); - - /* explicitly disable 10 bit mode & set 1 stop bit */ - tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); - - writel(tmp, ®->baud); -} - -static void serial_putc(struct lpuart_fsl_reg32* reg, const char c) { - u32 stat; - - while (1) { - lpuart_read32(®->stat, &stat); - - if (stat & STAT_TDRE) { - break; - } - } - - lpuart_write32(®->data, c); -} - -struct iomux { - u16 buf; - u8 mode; - u8 pull; -}; - - -void iomux() { - u32 pcc_u4; - struct iomux imu4; - - pcc_u4 = readl(0x403f00b4); - pcc_u4 |= (1 << 30); - writel(pcc_u4, 0x403f00b4); - - imu4.buf = 0b0011; // PTC2 U4 TX - imu4.mode = 0b0100; // PTC2 U4 TX - imu4.pull = 0b11; // PTC2 U4 TX - writel(*((u32 *)&imu4), (u32 *)0x40ac0008); - - //writel(0x0000000a, 0x400f0004); - - //writel(0x000fffff, 0x400f0004); - //writel(0x00000fff, 0x400f0044); - - //writel(0x0000ffff, 0x400f0084); - //writel(0x000fffff, 0x400f00c4); -} - void main() { - u32 ctrl, baud, i; - - writel(0x00000004, 0x400f0004); - - iomux(); - - lpuart_write32(®s[4]->global, 0); // De-assert reset:w - - lpuart_read32(®s[4]->baud, &baud); - baud &= ~(1 << 15); // LBKDIE - baud &= ~(1 << 14); // RXEDGIE - lpuart_write32(®s[4]->baud, baud); - - lpuart_read32(®s[4]->ctrl, &ctrl); - - ctrl &= ~CTRL_ORIE; - ctrl &= ~CTRL_NEIE; - ctrl &= ~CTRL_FEIE; - ctrl &= ~CTRL_PEIE; - ctrl &= ~CTRL_TIE; - ctrl &= ~CTRL_TCIE; - ctrl &= ~CTRL_RIE; - ctrl &= ~CTRL_ILIE; - ctrl &= ~CTRL_MA1IE; - ctrl &= ~CTRL_MA2IE; - - ctrl &= ~CTRL_RE; - ctrl &= ~CTRL_TE; - - lpuart_write32(®s[4]->ctrl, ctrl); - lpuart_write32(®s[4]->modir, 0); - lpuart_write32(®s[4]->fifo, ~(FIFO_TXFE | FIFO_RXFE)); - lpuart_write32(®s[4]->match, 0); - - setbrg(regs[4], 115200); - - ctrl |= CTRL_RE; - ctrl |= CTRL_TE; - - lpuart_write32(®s[4]->ctrl, ctrl); - - // putc - while (1) { - for (i=0; i<8; i++) { - serial_putc(regs[4], 'Y'); - serial_putc(regs[4], '\n'); - } + char *str = "Hello World"; + int aa = 1234; + int i; + for (i=0; i<999; i++) { + asm volatile( + "mrc p15, 0, r10, c1, c0, 0\n" + "bic r10, #1\n" + "mcr p15, 0, r10, c1, c0, 0\n" + : "=r" (aa) + ); + aa += 1; } - - asm volatile( - "mov pc, lr\n" - ); } diff --git a/x1/c/main.c.lcd b/x1/c/main.c.lcd deleted file mode 100644 index 86d697a..0000000 --- a/x1/c/main.c.lcd +++ /dev/null @@ -1,24 +0,0 @@ -#include "common.h" - -void main() { - u16** fb = (u16 **)0x62000000; - pixel_t px = { - .r = 255, - .g = 0, - .b = 0 - }; - - prepare_fb(fb); - writel(0x00000001, 0x40aa0008); // Clear RUN - writel(0x62000000, 0x40aa0040); // Set current FB - writel(0x62000000, 0x40aa0050); // Set next FB - writel(0x00000001, 0x40aa0004); // Set RUN - - //bitblt(fb, px, 100, 100); - - asm volatile( - "foo:\n" - "b foo\n" - "mov pc, lr\n" - ); -} diff --git a/x1/c/pcc.h b/x1/c/pcc.h deleted file mode 100644 index 0a6e0d4..0000000 --- a/x1/c/pcc.h +++ /dev/null @@ -1,371 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_PCC_H -#define _ASM_ARCH_PCC_H - -#include "scg.h" - -/* PCC2 */ - -enum pcc2_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC2_SLOT = 0, - RSVD1_PCC2_SLOT = 1, - CA7_GIC_PCC2_SLOT = 2, - RSVD3_PCC2_SLOT = 3, - RSVD4_PCC2_SLOT = 4, - RSVD5_PCC2_SLOT = 5, - RSVD6_PCC2_SLOT = 6, - RSVD7_PCC2_SLOT = 7, - DMA1_PCC2_SLOT = 8, - RSVD9_PCC2_SLOT = 9, - RSVD10_PCC2_SLOT = 10, - RSVD11_PCC2_SLOT = 11, - RSVD12_PCC2_SLOT = 12, - RSVD13_PCC2_SLOT = 13, - RSVD14_PCC2_SLOT = 14, - RGPIO1_PCC2_SLOT = 15, - FLEXBUS0_PCC2_SLOT = 16, - RSVD17_PCC2_SLOT = 17, - RSVD18_PCC2_SLOT = 18, - RSVD19_PCC2_SLOT = 19, - RSVD20_PCC2_SLOT = 20, - RSVD21_PCC2_SLOT = 21, - RSVD22_PCC2_SLOT = 22, - RSVD23_PCC2_SLOT = 23, - RSVD24_PCC2_SLOT = 24, - RSVD25_PCC2_SLOT = 25, - RSVD26_PCC2_SLOT = 26, - SEMA42_1_PCC2_SLOT = 27, - RSVD28_PCC2_SLOT = 28, - RSVD29_PCC2_SLOT = 29, - RSVD30_PCC2_SLOT = 30, - RSVD31_PCC2_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC2_SLOT = 32, - DMA1_CH_MUX0_PCC2_SLOT = 33, - MU_B_PCC2_SLOT = 34, - SNVS_PCC2_SLOT = 35, - CAAM_PCC2_SLOT = 36, - LPTPM4_PCC2_SLOT = 37, - LPTPM5_PCC2_SLOT = 38, - LPIT1_PCC2_SLOT = 39, - RSVD40_PCC2_SLOT = 40, - LPSPI2_PCC2_SLOT = 41, - LPSPI3_PCC2_SLOT = 42, - LPI2C4_PCC2_SLOT = 43, - LPI2C5_PCC2_SLOT = 44, - LPUART4_PCC2_SLOT = 45, - LPUART5_PCC2_SLOT = 46, - RSVD47_PCC2_SLOT = 47, - RSVD48_PCC2_SLOT = 48, - FLEXIO1_PCC2_SLOT = 49, - RSVD50_PCC2_SLOT = 50, - USBOTG0_PCC2_SLOT = 51, - USBOTG1_PCC2_SLOT = 52, - USBPHY_PCC2_SLOT = 53, - USB_PL301_PCC2_SLOT = 54, - USDHC0_PCC2_SLOT = 55, - USDHC1_PCC2_SLOT = 56, - RSVD57_PCC2_SLOT = 57, - TRGMUX1_PCC2_SLOT = 58, - RSVD59_PCC2_SLOT = 59, - RSVD60_PCC2_SLOT = 60, - WDG1_PCC2_SLOT = 61, - SCG1_PCC2_SLOT = 62, - PCC2_PCC2_SLOT = 63, - PMC1_PCC2_SLOT = 64, - SMC1_PCC2_SLOT = 65, - RCM1_PCC2_SLOT = 66, - WDG2_PCC2_SLOT = 67, - RSVD68_PCC2_SLOT = 68, - TEST_SPACE1_PCC2_SLOT = 69, - TEST_SPACE2_PCC2_SLOT = 70, - TEST_SPACE3_PCC2_SLOT = 71, - RSVD72_PCC2_SLOT = 72, - RSVD73_PCC2_SLOT = 73, - RSVD74_PCC2_SLOT = 74, - RSVD75_PCC2_SLOT = 75, - RSVD76_PCC2_SLOT = 76, - RSVD77_PCC2_SLOT = 77, - RSVD78_PCC2_SLOT = 78, - RSVD79_PCC2_SLOT = 79, - RSVD80_PCC2_SLOT = 80, - RSVD81_PCC2_SLOT = 81, - RSVD82_PCC2_SLOT = 82, - RSVD83_PCC2_SLOT = 83, - RSVD84_PCC2_SLOT = 84, - RSVD85_PCC2_SLOT = 85, - RSVD86_PCC2_SLOT = 86, - RSVD87_PCC2_SLOT = 87, - RSVD88_PCC2_SLOT = 88, - RSVD89_PCC2_SLOT = 89, - RSVD90_PCC2_SLOT = 90, - RSVD91_PCC2_SLOT = 91, - RSVD92_PCC2_SLOT = 92, - RSVD93_PCC2_SLOT = 93, - RSVD94_PCC2_SLOT = 94, - RSVD95_PCC2_SLOT = 95, - RSVD96_PCC2_SLOT = 96, - RSVD97_PCC2_SLOT = 97, - RSVD98_PCC2_SLOT = 98, - RSVD99_PCC2_SLOT = 99, - RSVD100_PCC2_SLOT = 100, - RSVD101_PCC2_SLOT = 101, - RSVD102_PCC2_SLOT = 102, - RSVD103_PCC2_SLOT = 103, - RSVD104_PCC2_SLOT = 104, - RSVD105_PCC2_SLOT = 105, - RSVD106_PCC2_SLOT = 106, - RSVD107_PCC2_SLOT = 107, - RSVD108_PCC2_SLOT = 108, - RSVD109_PCC2_SLOT = 109, - RSVD110_PCC2_SLOT = 110, - RSVD111_PCC2_SLOT = 111, - RSVD112_PCC2_SLOT = 112, - RSVD113_PCC2_SLOT = 113, - RSVD114_PCC2_SLOT = 114, - RSVD115_PCC2_SLOT = 115, - RSVD116_PCC2_SLOT = 116, - RSVD117_PCC2_SLOT = 117, - RSVD118_PCC2_SLOT = 118, - RSVD119_PCC2_SLOT = 119, - RSVD120_PCC2_SLOT = 120, - RSVD121_PCC2_SLOT = 121, - RSVD122_PCC2_SLOT = 122, - RSVD123_PCC2_SLOT = 123, - RSVD124_PCC2_SLOT = 124, - RSVD125_PCC2_SLOT = 125, - RSVD126_PCC2_SLOT = 126, - RSVD127_PCC2_SLOT = 127, -}; - -enum pcc3_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC3_SLOT = 0, - RSVD1_PCC3_SLOT = 1, - RSVD2_PCC3_SLOT = 2, - RSVD3_PCC3_SLOT = 3, - RSVD4_PCC3_SLOT = 4, - RSVD5_PCC3_SLOT = 5, - RSVD6_PCC3_SLOT = 6, - RSVD7_PCC3_SLOT = 7, - RSVD8_PCC3_SLOT = 8, - RSVD9_PCC3_SLOT = 9, - RSVD10_PCC3_SLOT = 10, - RSVD11_PCC3_SLOT = 11, - RSVD12_PCC3_SLOT = 12, - RSVD13_PCC3_SLOT = 13, - RSVD14_PCC3_SLOT = 14, - RSVD15_PCC3_SLOT = 15, - ROMCP1_PCC3_SLOT = 16, - RSVD17_PCC3_SLOT = 17, - RSVD18_PCC3_SLOT = 18, - RSVD19_PCC3_SLOT = 19, - RSVD20_PCC3_SLOT = 20, - RSVD21_PCC3_SLOT = 21, - RSVD22_PCC3_SLOT = 22, - RSVD23_PCC3_SLOT = 23, - RSVD24_PCC3_SLOT = 24, - RSVD25_PCC3_SLOT = 25, - RSVD26_PCC3_SLOT = 26, - RSVD27_PCC3_SLOT = 27, - RSVD28_PCC3_SLOT = 28, - RSVD29_PCC3_SLOT = 29, - RSVD30_PCC3_SLOT = 30, - RSVD31_PCC3_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC3_SLOT = 32, - LPTPM6_PCC3_SLOT = 33, - LPTPM7_PCC3_SLOT = 34, - RSVD35_PCC3_SLOT = 35, - LPI2C6_PCC3_SLOT = 36, - LPI2C7_PCC3_SLOT = 37, - LPUART6_PCC3_SLOT = 38, - LPUART7_PCC3_SLOT = 39, - VIU0_PCC3_SLOT = 40, - DSI0_PCC3_SLOT = 41, - LCDIF0_PCC3_SLOT = 42, - MMDC0_PCC3_SLOT = 43, - IOMUXC1_PCC3_SLOT = 44, - IOMUXC_DDR_PCC3_SLOT = 45, - PORTC_PCC3_SLOT = 46, - PORTD_PCC3_SLOT = 47, - PORTE_PCC3_SLOT = 48, - PORTF_PCC3_SLOT = 49, - RSVD50_PCC3_SLOT = 50, - PCC3_PCC3_SLOT = 51, - RSVD52_PCC3_SLOT = 52, - WKPU_PCC3_SLOT = 53, - RSVD54_PCC3_SLOT = 54, - RSVD55_PCC3_SLOT = 55, - RSVD56_PCC3_SLOT = 56, - RSVD57_PCC3_SLOT = 57, - RSVD58_PCC3_SLOT = 58, - RSVD59_PCC3_SLOT = 59, - RSVD60_PCC3_SLOT = 60, - RSVD61_PCC3_SLOT = 61, - RSVD62_PCC3_SLOT = 62, - RSVD63_PCC3_SLOT = 63, - RSVD64_PCC3_SLOT = 64, - RSVD65_PCC3_SLOT = 65, - RSVD66_PCC3_SLOT = 66, - RSVD67_PCC3_SLOT = 67, - RSVD68_PCC3_SLOT = 68, - RSVD69_PCC3_SLOT = 69, - RSVD70_PCC3_SLOT = 70, - RSVD71_PCC3_SLOT = 71, - RSVD72_PCC3_SLOT = 72, - RSVD73_PCC3_SLOT = 73, - RSVD74_PCC3_SLOT = 74, - RSVD75_PCC3_SLOT = 75, - RSVD76_PCC3_SLOT = 76, - RSVD77_PCC3_SLOT = 77, - RSVD78_PCC3_SLOT = 78, - RSVD79_PCC3_SLOT = 79, - RSVD80_PCC3_SLOT = 80, - GPU3D_PCC3_SLOT = 81, - GPU2D_PCC3_SLOT = 82, - RSVD83_PCC3_SLOT = 83, - RSVD84_PCC3_SLOT = 84, - RSVD85_PCC3_SLOT = 85, - RSVD86_PCC3_SLOT = 86, - RSVD87_PCC3_SLOT = 87, - RSVD88_PCC3_SLOT = 88, - RSVD89_PCC3_SLOT = 89, - RSVD90_PCC3_SLOT = 90, - RSVD91_PCC3_SLOT = 91, - RSVD92_PCC3_SLOT = 92, - RSVD93_PCC3_SLOT = 93, - RSVD94_PCC3_SLOT = 94, - RSVD95_PCC3_SLOT = 95, - RSVD96_PCC3_SLOT = 96, - RSVD97_PCC3_SLOT = 97, - RSVD98_PCC3_SLOT = 98, - RSVD99_PCC3_SLOT = 99, - RSVD100_PCC3_SLOT = 100, - RSVD101_PCC3_SLOT = 101, - RSVD102_PCC3_SLOT = 102, - RSVD103_PCC3_SLOT = 103, - RSVD104_PCC3_SLOT = 104, - RSVD105_PCC3_SLOT = 105, - RSVD106_PCC3_SLOT = 106, - RSVD107_PCC3_SLOT = 107, - RSVD108_PCC3_SLOT = 108, - RSVD109_PCC3_SLOT = 109, - RSVD110_PCC3_SLOT = 110, - RSVD111_PCC3_SLOT = 111, - RSVD112_PCC3_SLOT = 112, - RSVD113_PCC3_SLOT = 113, - RSVD114_PCC3_SLOT = 114, - RSVD115_PCC3_SLOT = 115, - RSVD116_PCC3_SLOT = 116, - RSVD117_PCC3_SLOT = 117, - RSVD118_PCC3_SLOT = 118, - RSVD119_PCC3_SLOT = 119, - RSVD120_PCC3_SLOT = 120, - RSVD121_PCC3_SLOT = 121, - RSVD122_PCC3_SLOT = 122, - RSVD123_PCC3_SLOT = 123, - RSVD124_PCC3_SLOT = 124, - RSVD125_PCC3_SLOT = 125, - RSVD126_PCC3_SLOT = 126, - RSVD127_PCC3_SLOT = 127, -}; - - -/* PCC registers */ -#define PCC_PR_OFFSET 31 -#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) -#define PCC_CGC_OFFSET 30 -#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) -#define PCC_INUSE_OFFSET 29 -#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) -#define PCC_PCS_OFFSET 24 -#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 4 -#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) -#define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) - - -enum pcc_clksrc_type { - CLKSRC_PER_PLAT = 0, - CLKSRC_PER_BUS = 1, - CLKSRC_NO_PCS = 2, -}; - -enum pcc_div_type { - PCC_HAS_DIV, - PCC_NO_DIV, -}; - -/* All peripheral clocks on A7 PCCs */ -enum pcc_clk { - /*PCC2 clocks*/ - PER_CLK_DMA1 = 0, - PER_CLK_RGPIO2P1, - PER_CLK_FLEXBUS, - PER_CLK_SEMA42_1, - PER_CLK_DMA_MUX1, - PER_CLK_SNVS, - PER_CLK_CAAM, - PER_CLK_LPTPM4, - PER_CLK_LPTPM5, - PER_CLK_LPIT1, - PER_CLK_LPSPI2, - PER_CLK_LPSPI3, - PER_CLK_LPI2C4, - PER_CLK_LPI2C5, - PER_CLK_LPUART4, - PER_CLK_LPUART5, - PER_CLK_FLEXIO1, - PER_CLK_USB0, - PER_CLK_USB1, - PER_CLK_USB_PHY, - PER_CLK_USB_PL301, - PER_CLK_USDHC0, - PER_CLK_USDHC1, - PER_CLK_WDG1, - PER_CLK_WDG2, - - /*PCC3 clocks*/ - PER_CLK_LPTPM6, - PER_CLK_LPTPM7, - PER_CLK_LPI2C6, - PER_CLK_LPI2C7, - PER_CLK_LPUART6, - PER_CLK_LPUART7, - PER_CLK_VIU, - PER_CLK_DSI, - PER_CLK_LCDIF, - PER_CLK_MMDC, - PER_CLK_PCTLC, - PER_CLK_PCTLD, - PER_CLK_PCTLE, - PER_CLK_PCTLF, - PER_CLK_GPU3D, - PER_CLK_GPU2D, -}; - - -/* This structure keeps info for each pcc slot */ -struct pcc_entry { - u32 pcc_base; - u32 pcc_slot; - enum pcc_clksrc_type clksrc; - enum pcc_div_type div; -}; - -int pcc_clock_enable(enum pcc_clk clk, int enable); -int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); -int pcc_clock_div_config(enum pcc_clk clk, int frac, u8 div); -int pcc_clock_is_enable(enum pcc_clk clk); -int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); -u32 pcc_clock_get_rate(enum pcc_clk clk); -#endif diff --git a/x1/c/scg.c b/x1/c/scg.c deleted file mode 100644 index 8d70c6d..0000000 --- a/x1/c/scg.c +++ /dev/null @@ -1,640 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include "common.h" -//#include -//#include -//#include -#include "imx-regs.h" -#include "pcc.h" -//#include - -scg_p scg1_regs = (scg_p)SCG1_RBASE; - -//////////////////////////////////////////////////////////////// -static u32 scg_src_get_rate(enum scg_clk clksrc) -{ - u32 reg; - - switch (clksrc) { - case SCG_SOSC_CLK: - reg = readl(&scg1_regs->sosccsr); - if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) - return 0; - - return 24000000; - case SCG_FIRC_CLK: - reg = readl(&scg1_regs->firccsr); - if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) - return 0; - - return 48000000; - case SCG_SIRC_CLK: - reg = readl(&scg1_regs->sirccsr); - if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) - return 0; - - return 16000000; - case SCG_ROSC_CLK: - reg = readl(&scg1_regs->rtccsr); - if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK)) - return 0; - - return 32768; - default: - break; - } - - return 0; -} - -////////////////////////////////////////////////////////////////////// -static u32 scg_sircdiv_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - u32 shift, mask; - - switch (clk) { - case SCG_SIRC_DIV1_CLK: - mask = SCG_SIRCDIV_DIV1_MASK; - shift = SCG_SIRCDIV_DIV1_SHIFT; - break; - case SCG_SIRC_DIV2_CLK: - mask = SCG_SIRCDIV_DIV2_MASK; - shift = SCG_SIRCDIV_DIV2_SHIFT; - break; - case SCG_SIRC_DIV3_CLK: - mask = SCG_SIRCDIV_DIV3_MASK; - shift = SCG_SIRCDIV_DIV3_SHIFT; - break; - default: - return 0; - } - - reg = readl(&scg1_regs->sirccsr); - if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) - return 0; - - reg = readl(&scg1_regs->sircdiv); - val = (reg & mask) >> shift; - - if (!val) /*clock disabled*/ - return 0; - - rate = scg_src_get_rate(SCG_SIRC_CLK); - rate = rate / (1 << (val - 1)); - - return rate; -} - -//////////////////////////////////////////////////////////////// -static u32 scg_fircdiv_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - u32 shift, mask; - - switch (clk) { - case SCG_FIRC_DIV1_CLK: - mask = SCG_FIRCDIV_DIV1_MASK; - shift = SCG_FIRCDIV_DIV1_SHIFT; - break; - case SCG_FIRC_DIV2_CLK: - mask = SCG_FIRCDIV_DIV2_MASK; - shift = SCG_FIRCDIV_DIV2_SHIFT; - break; - case SCG_FIRC_DIV3_CLK: - mask = SCG_FIRCDIV_DIV3_MASK; - shift = SCG_FIRCDIV_DIV3_SHIFT; - break; - default: - return 0; - } - - reg = readl(&scg1_regs->firccsr); - if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) - return 0; - - reg = readl(&scg1_regs->fircdiv); - val = (reg & mask) >> shift; - - if (!val) /*clock disabled*/ - return 0; - - rate = scg_src_get_rate(SCG_FIRC_CLK); - rate = rate / (1 << (val - 1)); - - return rate; -} - -/////////////////////////////////////////////////////////////////////// -static u32 scg_soscdiv_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - u32 shift, mask; - - switch (clk) { - case SCG_SOSC_DIV1_CLK: - mask = SCG_SOSCDIV_DIV1_MASK; - shift = SCG_SOSCDIV_DIV1_SHIFT; - break; - case SCG_SOSC_DIV2_CLK: - mask = SCG_SOSCDIV_DIV2_MASK; - shift = SCG_SOSCDIV_DIV2_SHIFT; - break; - case SCG_SOSC_DIV3_CLK: - mask = SCG_SOSCDIV_DIV3_MASK; - shift = SCG_SOSCDIV_DIV3_SHIFT; - break; - default: - return 0; - } - - reg = readl(&scg1_regs->sosccsr); - if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) - return 0; - - reg = readl(&scg1_regs->soscdiv); - val = (reg & mask) >> shift; - - if (!val) /*clock disabled*/ - return 0; - - rate = scg_src_get_rate(SCG_SOSC_CLK); - rate = rate / (1 << (val - 1)); - - return rate; -} - -/////////////////////////////////////////////////////////////// -static u32 scg_apll_pfd_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - u32 shift, mask, gate, valid; - - switch (clk) { - case SCG_APLL_PFD0_CLK: - gate = SCG_PLL_PFD0_GATE_MASK; - valid = SCG_PLL_PFD0_VALID_MASK; - mask = SCG_PLL_PFD0_FRAC_MASK; - shift = SCG_PLL_PFD0_FRAC_SHIFT; - break; - case SCG_APLL_PFD1_CLK: - gate = SCG_PLL_PFD1_GATE_MASK; - valid = SCG_PLL_PFD1_VALID_MASK; - mask = SCG_PLL_PFD1_FRAC_MASK; - shift = SCG_PLL_PFD1_FRAC_SHIFT; - break; - case SCG_APLL_PFD2_CLK: - gate = SCG_PLL_PFD2_GATE_MASK; - valid = SCG_PLL_PFD2_VALID_MASK; - mask = SCG_PLL_PFD2_FRAC_MASK; - shift = SCG_PLL_PFD2_FRAC_SHIFT; - break; - case SCG_APLL_PFD3_CLK: - gate = SCG_PLL_PFD3_GATE_MASK; - valid = SCG_PLL_PFD3_VALID_MASK; - mask = SCG_PLL_PFD3_FRAC_MASK; - shift = SCG_PLL_PFD3_FRAC_SHIFT; - break; - default: - return 0; - } - - reg = readl(&scg1_regs->apllpfd); - if (reg & gate || !(reg & valid)) - return 0; - - clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg); - - val = (reg & mask) >> shift; - rate = decode_pll(PLL_A7_APLL); - - rate = rate / val * 18; - - clk_debug("scg_apll_pfd_get_rate rate %u\n", rate); - - return rate; -} - -///////////////////////////////////////////////////////////////////nn -static u32 scg_spll_pfd_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - u32 shift, mask, gate, valid; - - switch (clk) { - case SCG_SPLL_PFD0_CLK: - gate = SCG_PLL_PFD0_GATE_MASK; - valid = SCG_PLL_PFD0_VALID_MASK; - mask = SCG_PLL_PFD0_FRAC_MASK; - shift = SCG_PLL_PFD0_FRAC_SHIFT; - break; - case SCG_SPLL_PFD1_CLK: - gate = SCG_PLL_PFD1_GATE_MASK; - valid = SCG_PLL_PFD1_VALID_MASK; - mask = SCG_PLL_PFD1_FRAC_MASK; - shift = SCG_PLL_PFD1_FRAC_SHIFT; - break; - case SCG_SPLL_PFD2_CLK: - gate = SCG_PLL_PFD2_GATE_MASK; - valid = SCG_PLL_PFD2_VALID_MASK; - mask = SCG_PLL_PFD2_FRAC_MASK; - shift = SCG_PLL_PFD2_FRAC_SHIFT; - break; - case SCG_SPLL_PFD3_CLK: - gate = SCG_PLL_PFD3_GATE_MASK; - valid = SCG_PLL_PFD3_VALID_MASK; - mask = SCG_PLL_PFD3_FRAC_MASK; - shift = SCG_PLL_PFD3_FRAC_SHIFT; - break; - default: - return 0; - } - - reg = readl(&scg1_regs->spllpfd); - if (reg & gate || !(reg & valid)) - return 0; - - clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg); - - val = (reg & mask) >> shift; - rate = decode_pll(PLL_A7_SPLL); - - rate = rate / val * 18; - - clk_debug("scg_spll_pfd_get_rate rate %u\n", rate); - - return rate; -} - -static u32 scg_apll_get_rate(void) -{ - u32 reg, val, rate; - - reg = readl(&scg1_regs->apllcfg); - val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; - - if (!val) { - /* APLL clock after two dividers */ - rate = decode_pll(PLL_A7_APLL); - - val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> - SCG_PLL_CFG_POSTDIV1_SHIFT; - rate = rate / (val + 1); - - val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> - SCG_PLL_CFG_POSTDIV2_SHIFT; - rate = rate / (val + 1); - } else { - /* APLL PFD clock */ - val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> - SCG_PLL_CFG_PFDSEL_SHIFT; - rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val); - } - - return rate; -} - -static u32 scg_spll_get_rate(void) -{ - u32 reg, val, rate; - - reg = readl(&scg1_regs->spllcfg); - val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; - - clk_debug("scg_spll_get_rate reg 0x%x\n", reg); - - if (!val) { - /* APLL clock after two dividers */ - rate = decode_pll(PLL_A7_SPLL); - - val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> - SCG_PLL_CFG_POSTDIV1_SHIFT; - rate = rate / (val + 1); - - val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> - SCG_PLL_CFG_POSTDIV2_SHIFT; - rate = rate / (val + 1); - - clk_debug("scg_spll_get_rate SPLL %u\n", rate); - - } else { - /* APLL PFD clock */ - val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> - SCG_PLL_CFG_PFDSEL_SHIFT; - rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val); - - clk_debug("scg_spll_get_rate PFD %u\n", rate); - } - - return rate; -} - -static enum scg_clk scg_scs_array[4] = { - SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK, -}; - -///////////////////////////////////////////////////////////////////// -static u32 scg_sys_get_rate(enum scg_clk clk) -{ - u32 reg, val, rate; - - if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK) - return 0; - - reg = readl(&scg1_regs->csr); - val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT; - - clk_debug("scg_sys_get_rate reg 0x%x\n", reg); - - switch (val) { - case SCG_SCS_SYS_OSC: - case SCG_SCS_SLOW_IRC: - case SCG_SCS_FAST_IRC: - case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); - break; - case 5: - rate = scg_apll_get_rate(); - break; - case 6: - rate = scg_spll_get_rate(); - break; - default: - return 0; - } - - clk_debug("scg_sys_get_rate parent rate %u\n", rate); - - val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT; - - rate = rate / (val + 1); - - if (clk == SCG_BUS_CLK) { - val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT; - rate = rate / (val + 1); - } - - return rate; -} - -/////////////////////////////////////////////////////////////// -u32 decode_pll(enum pll_clocks pll) -{ - u32 reg, pre_div, infreq, mult; - u32 num, denom; - - /* - * Alought there are four choices for the bypass src, - * we choose OSC_24M which is the default set in ROM. - */ - switch (pll) { - case PLL_A7_SPLL: - reg = readl(&scg1_regs->spllcsr); - - if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK)) - return 0; - - reg = readl(&scg1_regs->spllcfg); - - pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> - SCG_PLL_CFG_PREDIV_SHIFT; - pre_div += 1; - - mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >> - SCG_PLL_CFG_MULT_SHIFT; - - infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> - SCG_PLL_CFG_CLKSRC_SHIFT; - if (!infreq) - infreq = scg_src_get_rate(SCG_SOSC_CLK); - else - infreq = scg_src_get_rate(SCG_FIRC_CLK); - - num = readl(&scg1_regs->spllnum); - denom = readl(&scg1_regs->splldenom); - - infreq = infreq / pre_div; - - return infreq * mult + infreq * num / denom; - - case PLL_A7_APLL: - reg = readl(&scg1_regs->apllcsr); - - if (!(reg & SCG_APLL_CSR_APLLVLD_MASK)) - return 0; - - reg = readl(&scg1_regs->apllcfg); - - pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> - SCG_PLL_CFG_PREDIV_SHIFT; - pre_div += 1; - - mult = (reg & SCG_APLL_CFG_MULT_MASK) >> - SCG_PLL_CFG_MULT_SHIFT; - - infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> - SCG_PLL_CFG_CLKSRC_SHIFT; - if (!infreq) - infreq = scg_src_get_rate(SCG_SOSC_CLK); - else - infreq = scg_src_get_rate(SCG_FIRC_CLK); - - num = readl(&scg1_regs->apllnum); - denom = readl(&scg1_regs->aplldenom); - - infreq = infreq / pre_div; - - return infreq * mult + infreq * num / denom; - - case PLL_USB: - reg = readl(&scg1_regs->upllcsr); - - if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK)) - return 0; - - return 480000000u; - - case PLL_MIPI: - return 480000000u; - default: - break; - } - - return 0; -} - - -// ////////////////////////////////////////////////////////////////////////// -u32 scg_clk_get_rate(enum scg_clk clk) -{ - switch (clk) { - case SCG_SIRC_DIV1_CLK: - case SCG_SIRC_DIV2_CLK: - case SCG_SIRC_DIV3_CLK: - return scg_sircdiv_get_rate(clk); - - case SCG_FIRC_DIV1_CLK: - case SCG_FIRC_DIV2_CLK: - case SCG_FIRC_DIV3_CLK: - return scg_fircdiv_get_rate(clk); - - case SCG_SOSC_DIV1_CLK: - case SCG_SOSC_DIV2_CLK: - case SCG_SOSC_DIV3_CLK: - return scg_soscdiv_get_rate(clk); - - case SCG_CORE_CLK: - case SCG_BUS_CLK: - return scg_sys_get_rate(clk); - - case SCG_SPLL_PFD0_CLK: - case SCG_SPLL_PFD1_CLK: - case SCG_SPLL_PFD2_CLK: - case SCG_SPLL_PFD3_CLK: - return scg_spll_pfd_get_rate(clk); - - case SCG_APLL_PFD0_CLK: - case SCG_APLL_PFD1_CLK: - case SCG_APLL_PFD2_CLK: - case SCG_APLL_PFD3_CLK: - return scg_apll_pfd_get_rate(clk); - - case USB_PLL_OUT: - return decode_pll(PLL_USB); - - case MIPI_PLL_OUT: - return decode_pll(PLL_MIPI); - - case SCG_SOSC_CLK: - case SCG_FIRC_CLK: - case SCG_SIRC_CLK: - case SCG_ROSC_CLK: - return scg_src_get_rate(clk); - default: - return 0; - } -} - -/* A7 domain system clock source is SPLL */ -#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT) - -/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */ -#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT) -#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK) - -/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */ -#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT) -#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM) - -/* POSTDIV2 = 1 */ -#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) -/* POSTDIV1 = 1 */ -#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) - -/* MULT = 22 */ -#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) - -/* PFD0 output clock selected */ -#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) -/* PREDIV = 1 */ -#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) -/* SPLL output clocks (including PFD outputs) selected */ -#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) -/* SPLL PFD output clock selected */ -#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT) -/* Clock source is System OSC */ -#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) -#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \ - SCG1_SPLL_CFG_POSTDIV1_NUM | \ - (22 << SCG_PLL_CFG_MULT_SHIFT) | \ - SCG1_SPLL_CFG_PFDSEL_NUM | \ - SCG1_SPLL_CFG_PREDIV_NUM | \ - SCG1_SPLL_CFG_BYPASS_NUM | \ - SCG1_SPLL_CFG_PLLSEL_NUM | \ - SCG1_SPLL_CFG_CLKSRC_NUM) -/*413Mhz = A7 SPLL(528MHz) * 18/23 */ -#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT) - -/* DDR clock source is APLL PFD0 (396MHz) */ -#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT) -/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */ -#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT) -/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */ -#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT) -#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \ - SCG1_DDRCCR_DDRDIV_NUM) -#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \ - SCG1_DDRCCR_DDRDIV_LF_NUM) - -/* SCG1(A7) APLLCFG configurations */ -/* divide by 1 <<28 */ -#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) -/* divide by 1 <<24 */ -#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) -/* MULT is 22 <<16 */ -#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) -/* PFD0 output clock selected <<14 */ -#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) -/* PREDIV = 1 <<8 */ -#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) -/* APLL output clocks (including PFD outputs) selected <<2 */ -#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) -/* APLL PFD output clock selected <<1 */ -#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT) -/* Clock source is System OSC <<0 */ -#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) - -/* - * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz, - * system PLL is sourced from APLL, - * APLL clock source is system OSC (24MHz) - */ -#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \ - SCG1_APLL_CFG_POSTDIV1_NUM | \ - (22 << SCG_PLL_CFG_MULT_SHIFT) | \ - SCG1_APLL_CFG_PFDSEL_NUM | \ - SCG1_APLL_CFG_PREDIV_NUM | \ - SCG1_APLL_CFG_BYPASS_NUM | \ - SCG1_APLL_CFG_PLLSEL_NUM | \ - SCG1_APLL_CFG_CLKSRC_NUM) - -/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */ -#define SCG1_APLL_PFD0_FRAC_NUM (27) - - -/* SCG1(A7) FIRC DIV configurations */ -/* Disable FIRC DIV3 */ -#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT) -/* FIRC DIV2 = 48MHz / 1 = 48MHz */ -#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT) -/* Disable FIRC DIV1 */ -#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT) - -/* SCG1(A7) NICCCR configurations */ -/* NIC clock source is DDR clock (396/198MHz) */ -#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT) - -/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */ -#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT) -/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */ -#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT) -/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */ -#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT) -/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */ -#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) -#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \ - SCG1_NICCCR_NIC0_DIV_NUM | \ - SCG1_NICCCR_NIC1_DIV_NUM | \ - SCG1_NICCCR_NIC1_DIVBUS_NUM) - -/* SCG1(A7) FIRC DIV configurations */ -/* Enable FIRC DIV3 */ -#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT) -/* FIRC DIV2 = 48MHz / 1 = 48MHz */ -#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT) -/* Enable FIRC DIV1 */ -#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT) - diff --git a/x1/c/scg.h b/x1/c/scg.h deleted file mode 100644 index 2d25541..0000000 --- a/x1/c/scg.h +++ /dev/null @@ -1,339 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_SCG_H -#define _ASM_ARCH_SCG_H - -#ifdef CONFIG_CLK_DEBUG -#define clk_debug(fmt, args...) printf(fmt, ##args) -#else -#define clk_debug(fmt, args...) -#endif - -#define SCG_CCR_SCS_SHIFT (24) -#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT) -#define SCG_CCR_DIVCORE_SHIFT (16) -#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT) -#define SCG_CCR_DIVPLAT_SHIFT (12) -#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT) -#define SCG_CCR_DIVEXT_SHIFT (8) -#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT) -#define SCG_CCR_DIVBUS_SHIFT (4) -#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT) -#define SCG_CCR_DIVSLOW_SHIFT (0) -#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT) - -/* SCG DDR Clock Control Register */ -#define SCG_DDRCCR_DDRCS_SHIFT (24) -#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT) - -#define SCG_DDRCCR_DDRDIV_SHIFT (0) -#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT) - -/* SCG NIC Clock Control Register */ -#define SCG_NICCCR_NICCS_SHIFT (28) -#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT) - -#define SCG_NICCCR_NIC0_DIV_SHIFT (24) -#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT) - -#define SCG_NICCCR_GPU_DIV_SHIFT (20) -#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT) - -#define SCG_NICCCR_NIC1_DIV_SHIFT (16) -#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT) - -#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8) -#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT) - -#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4) -#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) - -/* SCG NIC clock status register */ -#define SCG_NICCSR_NICCS_SHIFT (28) -#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT) - -#define SCG_NICCSR_NIC0DIV_SHIFT (24) -#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT) -#define SCG_NICCSR_GPUDIV_SHIFT (20) -#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT) -#define SCG_NICCSR_NIC1DIV_SHIFT (16) -#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT) -#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8) -#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT) -#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4) -#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT) - -/* SCG Slow IRC Control Status Register */ -#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24) -#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT) - -#define SCG_SIRC_CSR_SIRCEN_SHIFT (0) -#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT) - -/* SCG Slow IRC Configuration Register */ -#define SCG_SIRCCFG_RANGE_SHIFT (0) -#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) -#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT) -#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) - -/* SCG Slow IRC Divide Register */ -#define SCG_SIRCDIV_DIV3_SHIFT (16) -#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT) - -#define SCG_SIRCDIV_DIV2_SHIFT (8) -#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT) - -#define SCG_SIRCDIV_DIV1_SHIFT (0) -#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT) -/* - * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK - * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK - * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK - */ - -/* SCG Fast IRC Control Status Register */ -#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24) -#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT) - -#define SCG_FIRC_CSR_FIRCEN_SHIFT (0) -#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT) - -/* SCG Fast IRC Divide Register */ -#define SCG_FIRCDIV_DIV3_SHIFT (16) -#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT) - -#define SCG_FIRCDIV_DIV2_SHIFT (8) -#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT) - -#define SCG_FIRCDIV_DIV1_SHIFT (0) -#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT) - -#define SCG_FIRCCFG_RANGE_SHIFT (0) -#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT) - -#define SCG_FIRCCFG_RANGE_SHIFT (0) -#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT) - -/* SCG System OSC Control Status Register */ -#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24) -#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT) - -/* SCG Fast IRC Divide Register */ -#define SCG_SOSCDIV_DIV3_SHIFT (16) -#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT) - -#define SCG_SOSCDIV_DIV2_SHIFT (8) -#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT) - -#define SCG_SOSCDIV_DIV1_SHIFT (0) -#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT) - -/* SCG RTC OSC Control Status Register */ -#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24) -#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT) - -#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24) -#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT) -#define SCG_SPLL_CSR_SPLLEN_SHIFT (0) -#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT) -#define SCG_APLL_CSR_APLLEN_SHIFT (0) -#define SCG_APLL_CSR_APLLEN_MASK (0x1UL) -#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000) - -#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) - - -#define SCG_PLL_PFD3_GATE_MASK (0x80000000) -#define SCG_PLL_PFD2_GATE_MASK (0x00800000) -#define SCG_PLL_PFD1_GATE_MASK (0x00008000) -#define SCG_PLL_PFD0_GATE_MASK (0x00000080) -#define SCG_PLL_PFD3_VALID_MASK (0x40000000) -#define SCG_PLL_PFD2_VALID_MASK (0x00400000) -#define SCG_PLL_PFD1_VALID_MASK (0x00004000) -#define SCG_PLL_PFD0_VALID_MASK (0x00000040) - -#define SCG_PLL_PFD0_FRAC_SHIFT (0) -#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT) -#define SCG_PLL_PFD1_FRAC_SHIFT (8) -#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT) -#define SCG_PLL_PFD2_FRAC_SHIFT (16) -#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT) -#define SCG_PLL_PFD3_FRAC_SHIFT (24) -#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT) - -#define SCG_PLL_CFG_POSTDIV2_SHIFT (28) -#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT) -#define SCG_PLL_CFG_POSTDIV1_SHIFT (24) -#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT) -#define SCG_PLL_CFG_MULT_SHIFT (16) -#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) -#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) -#define SCG_PLL_CFG_PFDSEL_SHIFT (14) -#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT) -#define SCG_PLL_CFG_PREDIV_SHIFT (8) -#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT) -#define SCG_PLL_CFG_BYPASS_SHIFT (2) -/* 0: SPLL, 1: bypass */ -#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT) -#define SCG_PLL_CFG_PLLSEL_SHIFT (1) -/* 0: pll, 1: pfd */ -#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) -#define SCG_PLL_CFG_CLKSRC_SHIFT (0) -/* 0: Sys-OSC, 1: FIRC */ -#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT) -#define SCG0_SPLL_CFG_MULT_SHIFT (17) -/* 0: Multiplier = 20, 1: Multiplier = 22 */ -#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT) - -#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) -#define PLL_USB_PWR_MASK (0x01 << 12) -#define PLL_USB_ENABLE_MASK (0x01 << 13) -#define PLL_USB_BYPASS_MASK (0x01 << 16) -#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) -#define PLL_USB_DIV_SEL_MASK (0x07 << 22) -#define PLL_USB_LOCK_MASK (0x01 << 31) - -enum scg_clk { - SCG_SOSC_CLK, - SCG_FIRC_CLK, - SCG_SIRC_CLK, - SCG_ROSC_CLK, - SCG_SIRC_DIV1_CLK, - SCG_SIRC_DIV2_CLK, - SCG_SIRC_DIV3_CLK, - SCG_FIRC_DIV1_CLK, - SCG_FIRC_DIV2_CLK, - SCG_FIRC_DIV3_CLK, - SCG_SOSC_DIV1_CLK, - SCG_SOSC_DIV2_CLK, - SCG_SOSC_DIV3_CLK, - SCG_CORE_CLK, - SCG_BUS_CLK, - SCG_SPLL_PFD0_CLK, - SCG_SPLL_PFD1_CLK, - SCG_SPLL_PFD2_CLK, - SCG_SPLL_PFD3_CLK, - SCG_DDR_CLK, - SCG_NIC0_CLK, - SCG_GPU_CLK, - SCG_NIC1_CLK, - SCG_NIC1_BUS_CLK, - SCG_NIC1_EXT_CLK, - SCG_APLL_PFD0_CLK, - SCG_APLL_PFD1_CLK, - SCG_APLL_PFD2_CLK, - SCG_APLL_PFD3_CLK, - USB_PLL_OUT, - MIPI_PLL_OUT -}; - -enum scg_sys_src { - SCG_SCS_SYS_OSC = 1, - SCG_SCS_SLOW_IRC, - SCG_SCS_FAST_IRC, - SCG_SCS_RTC_OSC, - SCG_SCS_AUX_PLL, - SCG_SCS_SYS_PLL, - SCG_SCS_USBPHY_PLL, -}; - -/* PLL supported by i.mx7ulp */ -enum pll_clocks { - PLL_M4_SPLL, /* M4 SPLL */ - PLL_M4_APLL, /* M4 APLL*/ - PLL_A7_SPLL, /* A7 SPLL */ - PLL_A7_APLL, /* A7 APLL */ - PLL_USB, /* USB PLL*/ - PLL_MIPI, /* MIPI PLL */ -}; - -typedef struct scg_regs { - u32 verid; /* VERSION_ID */ - u32 param; /* PARAMETER */ - u32 rsvd11[2]; - - u32 csr; /* Clock Status Register */ - u32 rccr; /* Run Clock Control Register */ - u32 vccr; /* VLPR Clock Control Register */ - u32 hccr; /* HSRUN Clock Control Register */ - u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */ - u32 rsvd12[3]; - u32 ddrccr; /* SCG DDR Clock Control Register */ - u32 rsvd13[3]; - u32 nicccr; /* NIC Clock Control Register */ - u32 niccsr; /* NIC Clock Status Register */ - u32 rsvd10[46]; - - u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */ - u32 soscdiv; /* System OSC Divide Register */ - u32 sosccfg; /* System Oscillator Configuration Register */ - u32 sosctest; /* System Oscillator Test Register */ - u32 rsvd20[60]; - - u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */ - u32 sircdiv; /* Slow IRC Divide Register */ - u32 sirccfg; /* Slow IRC Configuration Register */ - u32 sirctrim; /* Slow IRC Trim Register */ - u32 loptrim; /* Low Power Oscillator Trim Register */ - u32 sirctest; /* Slow IRC Test Register */ - u32 rsvd30[58]; - - u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */ - u32 fircdiv; - u32 firccfg; - u32 firctcfg; /* Fast IRC Trim Configuration Register */ - u32 firctriml; /* Fast IRC Trim Low Register */ - u32 firctrimh; - u32 fircstat; /* Fast IRC Status Register */ - u32 firctest; /* Fast IRC Test Register */ - u32 rsvd40[56]; - - u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */ - u32 rsvd50[63]; - - u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ - u32 aplldiv; /* Auxiliary PLL Divider Register */ - u32 apllcfg; /* Auxiliary PLL Configuration Register */ - u32 apllpfd; /* Auxiliary PLL PFD Register */ - u32 apllnum; /* Auxiliary PLL Numerator Register */ - u32 aplldenom; /* Auxiliary PLL Denominator Register */ - u32 apllss; /* Auxiliary PLL Spread Spectrum Register */ - u32 rsvd60[55]; - u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */ - u32 rsvd61[1]; - - u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */ - u32 splldiv; /* System PLL Divide Register */ - u32 spllcfg; /* System PLL Configuration Register */ - u32 spllpfd; /* System PLL Test Register */ - u32 spllnum; /* System PLL Numerator Register */ - u32 splldenom; /* System PLL Denominator Register */ - u32 spllss; /* System PLL Spread Spectrum Register */ - u32 rsvd70[55]; - u32 spllock_cnfg; /* System PLL LOCK Configuration Register */ - u32 rsvd71[1]; - - u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */ - u32 uplldiv; /* USB PLL Divide Register */ - u32 upllcfg; /* USB PLL Configuration Register */ -} scg_t, *scg_p; - -u32 scg_clk_get_rate(enum scg_clk clk); -int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); -//int scg_enable_usb_pll(bool usb_control); -u32 decode_pll(enum pll_clocks pll); - -void scg_a7_rccr_init(void); -void scg_a7_spll_init(void); -void scg_a7_ddrclk_init(void); -void scg_a7_apll_init(void); -void scg_a7_firc_init(void); -void scg_a7_nicclk_init(void); -void scg_a7_sys_clk_sel(enum scg_sys_src clk); -void scg_a7_info(void); -void scg_a7_soscdiv_init(void); - -#endif diff --git a/x1/c/sizes.h b/x1/c/sizes.h deleted file mode 100644 index ce3e815..0000000 --- a/x1/c/sizes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * include/linux/sizes.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __LINUX_SIZES_H__ -#define __LINUX_SIZES_H__ - -#define SZ_1 0x00000001 -#define SZ_2 0x00000002 -#define SZ_4 0x00000004 -#define SZ_8 0x00000008 -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __LINUX_SIZES_H__ */ diff --git a/x1/injector/disable_mmu.elf b/x1/injector/disable_mmu.elf new file mode 100644 index 0000000000000000000000000000000000000000..e696f776906073f0d3a1106003ea793faf41632d GIT binary patch literal 624 zcma)(O-chn5QSem{)`|paV6+R2$+R5E?m0FLRSjn1*C@=Gz&qdThNs`f;Vt(kb8Iw zNwN*%39OfyiXAul;N?}(A5}e_m$Qp=V+>RVJ^XaQanr1w%z++KYyhwIcnfdSY}A>V z`hA>@%nYCP2Qa+tcLa2$%Lgz*B8`XXk|>j3$!eCX1-37J0AdyqSczxLh(+P2Oo0%BKKZxZq%O?_vAbm)3<)4f4lOdL8rN>#5pT0-rStf=$K03nrwU0b_YIZ;E}8%U literal 0 HcmV?d00001 diff --git a/x1/injector/injected.elf b/x1/injector/injected.elf new file mode 100644 index 0000000000000000000000000000000000000000..aab7ec51b3ee6a3f4f3610ce6cb325424a578035 GIT binary patch literal 584 zcmah`F>V4e5FE!44yA##sUjgk5xGj4h9XoTp?o0niIbo}iq4A!RldSg=<|vwAIKB3 zb7$v{C=zp8&#XOO@7eFq^O-RQ2?i518IaXU_pvfekfEpQ_=WG|=X9vj7e3#>a5j1? z=YNAes|;9No!P9;w9m$$%%Y=Tg8|n^9l{jhKP(-A9eB!q6L-Y2(B;OCJfh0x% literal 0 HcmV?d00001