2021-03-06 20:32:14 +09:00
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.text
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.align 2
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.global _start
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_start:
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ldr r0, =0x67800000
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2021-03-10 00:32:07 +09:00
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cpsid if
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mrc p15, 0, r8, c14, c2, 1
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bic r8, r8, #1
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mcr p15, 0, r8, c14, c2, 1
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mrc p15, 0, r8, c14, c3, 1
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bic r8, r8, #1
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mcr p15, 0, r8, c14, c3, 1
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mov r9, #0
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2021-03-06 20:32:14 +09:00
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mrc p15, 0, r10, c1, c0, 0
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@bic r10, r10, #5 @ disable MMU and dcache
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bic r10, r10, #1 @ disable MMU
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@bic r10, r10, #4096 @ disable icache
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mcr p15, 0, r10, c1, c0, 0 // write ctrl regs
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#mcr p15, 0, r9, c7, c7, 0 // invalidate cache
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#mcr p15, 0, r9, c8, c7, 0 // invalidate TLB
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mov pc, r0
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