mirror of
https://github.com/brain-hackers/brainlilo
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98a6ae1c54
* Add support 1st generation Brain Address information was given by pepepper. Thank you! * Use CamelCase to name enum types * Update BrainLILODrv.cpp Co-authored-by: Takumi Sueda <puhitaku@gmail.com> * simplify BrainGen enum types * Remove redundant debu log * Fix Gen2 and later addresses Co-authored-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com> Co-authored-by: Toshifumi NISHINAGA <tnishinaga@users.noreply.github.com> Co-authored-by: pepepper <hollyholly2014@outlook.jp>
31 lines
660 B
ArmAsm
31 lines
660 B
ArmAsm
.align 4
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.global EDNA2_physicalInvoker
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EDNA2_physicalInvoker:
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// r0-r7=params
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// r8=proc address
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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msr cpsr_c, #211 // to supervisor mode
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mov r9, #0
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mcr p15,0,r9,c13,c0,0 // clear fcse PID
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mrc p15,0,r9,c1,c0,0 // read ctrl regs
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bic r9, r9, #5 // disable MMU/DCache
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bic r9, r9, #4096 // disable ICache
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orr r9, r9, #8192 // and reset vectors to upper
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mcr p15,0,r9,c1,c0,0 // write ctrl regs
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mov r9, #0
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mcr p15,0,r9,c7,c7,0 // invalidate cache
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mcr p15,0,r9,c8,c7,0 // invalidate tlb
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mov pc, r8
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nop
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nop
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