brain-hackers_pepepper-mirror/brainlilo
1
0
Fork 0
mirror of https://github.com/brain-hackers/brainlilo synced 2026-09-22 07:32:12 +09:00
Code Issues Projects Releases Wiki Activity

Add support 1st generation Brain (#9)

Browse Source 
* Add support 1st generation Brain

Address information was given by pepepper.
Thank you!

* Use CamelCase to name enum types

* Update BrainLILODrv.cpp

Co-authored-by: Takumi Sueda <[email protected]>

* simplify BrainGen enum types

* Remove redundant debu log

* Fix Gen2 and later addresses

Co-authored-by: Toshifumi NISHINAGA <[email protected]>
Co-authored-by: Toshifumi NISHINAGA <[email protected]>
Co-authored-by: pepepper <[email protected]>
This commit is contained in:
Takumi Sueda
2022-09-23 00:41:59 +09:00
committed by GitHub
co-authored by Toshifumi NISHINAGA Toshifumi NISHINAGA pepepper
parent c826f2581e
commit 98a6ae1c54
5 changed files with 138 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files
EDNA2_physicalInvoker.S
+30
View File
@@ -0,0 +1,30 @@
.align 4
.global EDNA2_physicalInvoker
EDNA2_physicalInvoker:
// r0-r7=params
// r8=proc address
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
msr cpsr_c, #211 // to supervisor mode
mov r9, #0
mcr p15,0,r9,c13,c0,0 // clear fcse PID
mrc p15,0,r9,c1,c0,0 // read ctrl regs
bic r9, r9, #5 // disable MMU/DCache
bic r9, r9, #4096 // disable ICache
orr r9, r9, #8192 // and reset vectors to upper
mcr p15,0,r9,c1,c0,0 // write ctrl regs
mov r9, #0
mcr p15,0,r9,c7,c7,0 // invalidate cache
mcr p15,0,r9,c8,c7,0 // invalidate tlb
mov pc, r8
nop
nop